公开(公告)号：US20140353716A1

公开(公告)日：2014-12-04

申请号：US13906789

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成翅片掩模层，在鳍掩模层上形成虚拟栅极，以及在虚拟栅极的相对侧上形成源极和漏极区域。 去除虚拟栅极并且使用底层翅片掩模层来在半导体层中限定多个散热片。 在多个翅片上形成闸门。

公开(公告)号：US20170170299A1

公开(公告)日：2017-06-15

申请号：US15437487

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： STEPHANE ALLEGRET-MARET ,  KANGGUO CHENG ,  BRUCE DORIS ,  PRASANNA KHARE ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

公开(公告)号：US20170179137A1

公开(公告)日：2017-06-22

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： STEPHANE ALLEGRET-MARET ,  KANGGUO CHENG ,  BRUCE DORIS ,  PRASANNA KHARE ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US20160111338A1

公开(公告)日：2016-04-21

申请号：US14969393

申请日：2015-12-15

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE ,  QING LIU

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract translation: 描述了用于在体基板上将诸如Si和SiGe的两种半导体材料类型的finFET共集成的方法。 用于finFET的鳍可以形成在第一半导体类型的外延层中，并被绝缘体覆盖。 可以去除一部分翅片以在绝缘体中形成空隙，并且可以通过在空隙中外延生长第二类型的半导体材料来填充空隙。 共同集成的finFET可以形成在相同的器件级。

公开(公告)号：US20150303285A1

公开(公告)日：2015-10-22

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  PRASANNA KHARE ,  NICOLAS LOUBET

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract translation: 多鳍FINFET器件可以包括衬底和从衬底向上延伸并沿着衬底间隔开的多个半导体鳍片。 每个半导体鳍片可以具有相对的第一和第二端以及它们之间的中间部分，并且多个半导体鳍片的最外面的鳍片可以在其外表面上包括外延生长阻挡层。 FINFET还可以包括覆盖半导体鳍片的中间部分的至少一个栅极，在与其第一端相邻的半导体鳍片之间的多个凸起的外延半导体源极区域和在相邻的半导体鳍片之间的多个凸起的外延半导体漏极区域 其第二端。