公开(公告)号：US10833094B2

公开(公告)日：2020-11-10

申请号：US15954874

申请日：2018-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US12035643B2

公开(公告)日：2024-07-09

申请号：US17488026

申请日：2021-09-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yann Canvel ,  Sebastien Lagrasta ,  Sebastien Barnola ,  Christelle Boixaderas

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

公开(公告)号：US10128295B2

公开(公告)日：2018-11-13

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US20180076250A1

公开(公告)日：2018-03-15

申请号：US15263922

申请日：2016-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US20170186759A1

公开(公告)日：2017-06-29

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US11495609B2

公开(公告)日：2022-11-08

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20200098989A1

公开(公告)日：2020-03-26

申请号：US16578022

申请日：2019-09-20

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Yann Canvel ,  Sebastien Lagrasta ,  Sebastien Barnola ,  Christelle Boixaderas

IPC: H01L45/00

Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.

公开(公告)号：US20180158861A1

公开(公告)日：2018-06-07

申请号：US15866995

申请日：2018-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

公开(公告)号：US09978764B2

公开(公告)日：2018-05-22

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L27/11546 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L49/02 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/11541

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US09917126B1

公开(公告)日：2018-03-13

申请号：US15263922

申请日：2016-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Lagrasta ,  Delia Ristoiu ,  Jean-Pierre Oddou ,  Cécile Jenny

IPC: H01L31/062 ,  H01L31/113 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.