公开(公告)号：US11581304B2

公开(公告)日：2023-02-14

申请号：US16987066

申请日：2020-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory

IPC: H01L27/02 ,  H01L29/06

Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.

公开(公告)号：US11437365B2

公开(公告)日：2022-09-06

申请号：US16834329

申请日：2020-03-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric Laconde ,  Olivier Ory

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/87

Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.

公开(公告)号：US11289391B2

公开(公告)日：2022-03-29

申请号：US16802325

申请日：2020-02-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory

IPC: H01L23/31 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/78 ,  H01L29/861

Abstract: A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.

公开(公告)号：US09543247B1

公开(公告)日：2017-01-10

申请号：US15051158

申请日：2016-02-23

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory

IPC: H01L23/52 ,  H01L29/06 ,  H01L29/16 ,  H01L23/528 ,  H01L21/306 ,  H01L21/304 ,  H01L21/302 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/76843 ,  H01L21/302 ,  H01L21/3043 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/16 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.

Abstract translation: 表面安装芯片由具有正面和侧面的硅基板形成。 芯片包括用于焊接到外部设备的金属化。 金属化具有覆盖基板的前表面的至少一部分的第一部分和覆盖基板侧面的至少一部分的第二部分。 衬底中包括多孔硅区域以将金属化的第二部分与衬底的其余部分分离。

公开(公告)号：US08953290B2

公开(公告)日：2015-02-10

申请号：US13955112

申请日：2013-07-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory ,  Eric Laconde

IPC: H02H9/00 ,  H01L23/62 ,  H01L27/02

CPC classification number: H01L23/62 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.

Abstract translation: 一种用于保护集成电路免受过电压的装置，该装置形成在第一导电类型的半导体衬底的内部和顶部，并且包括：电容器，包括穿透到衬底中的第二导电类型的阱和形成有绝缘壁的沟槽 在井中充满导电材料; 以及由衬底和阱之间的接合部形成的齐纳二极管。

公开(公告)号：US11824028B2

公开(公告)日：2023-11-21

申请号：US17458070

申请日：2021-08-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Christophe Lebrere

IPC: H01L25/10 ,  H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/11916 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/8185 ,  H01L2224/81801

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US20140036399A1

公开(公告)日：2014-02-06

申请号：US13955112

申请日：2013-07-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory ,  Eric Laconde

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.

Abstract translation: 一种用于保护集成电路免受过电压的装置，该装置形成在第一导电类型的半导体衬底的内部和顶部，并且包括：电容器，包括穿透到衬底中的第二导电类型的阱和形成有绝缘壁的沟槽 在井中充满导电材料; 以及由衬底和阱之间的接合部形成的齐纳二极管。

公开(公告)号：US11881413B2

公开(公告)日：2024-01-23

申请号：US18153929

申请日：2023-01-12

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Michael De Cruz ,  Olivier Ory

IPC: H01L21/4763 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11574816B2

公开(公告)日：2023-02-07

申请号：US17104869

申请日：2020-11-25

Applicant: STMicroelectronics (Tours) SAS

Inventor： Michael De Cruz ,  Olivier Ory

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56

Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11158556B2

公开(公告)日：2021-10-26

申请号：US16552464

申请日：2019-08-27

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Romain Jaillet

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.