公开(公告)号：US09735772B2

公开(公告)日：2017-08-15

申请号：US14865618

申请日：2015-09-25

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H01L25/00 ,  H03K17/687 ,  H01L21/66 ,  G01R31/28 ,  H01L27/02

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US20150118805A1

公开(公告)日：2015-04-30

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20170288664A1

公开(公告)日：2017-10-05

申请号：US15630469

申请日：2017-06-22

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H03K17/687 ,  H01L27/02 ,  G01R31/28 ,  H01L21/66

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US20160134282A1

公开(公告)日：2016-05-12

申请号：US14865618

申请日：2015-09-25

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alexandre DRAY ,  Emmanuel Josse

IPC: H03K17/687 ,  G01R31/28 ,  H01L21/66

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

Abstract translation: 集成电路包括设置在集成电路的位置处的至少一个集成电池。 所述至少一个集成单元可以具有耦合到所述集成单元的至少一个站点和多路复用器的两个集成设备，并且所述两个集成设备分别定向在两个不同的取向方向上。 可以使用在两个取向方向中的一个方向上定向的两个集成装置的第一集成装置。 集成电路可以包括被配置为检测定向方向的控制器，其考虑到位置处的集成单元的布置可允许第一集成设备可用，并且控制多路复用器将第一集成设备 电连接至该至少一个位点。

公开(公告)号：US09318372B2

公开(公告)日：2016-04-19

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

公开(公告)号：US09543214B2

公开(公告)日：2017-01-10

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US09305828B2

公开(公告)日：2016-04-05

申请号：US14526005

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。

公开(公告)号：US20150118824A1

公开(公告)日：2015-04-30

申请号：US14526005

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。

公开(公告)号：US20150118823A1

公开(公告)日：2015-04-30

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

公开(公告)号：US20170117296A1

公开(公告)日：2017-04-27

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.