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1.发明公开公开(公告)号：US20240176863A1
公开(公告)日：2024-05-30
申请号：US18514795
申请日：2023-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Grand Quest) SAS , STMicroelectronics (Alps) SAS
Inventor： Fabrice Cheruel , Dragos Davidescu , Nicolas Anquet
Abstract: The system-on-chip includes at least one microprocessor domain including a microprocessor and at least one resource; and a resource isolation system including a filtering circuit for each resource and configured to detect a security, privilege and compartmentalization access rights violation for the resource, by transactions arriving at the resource. The filtering circuit is configured, in the event of a violation of at least one access right to the resource by a transaction, to generate a first error signal representative of the violated access right to the resource, and a second error signal representative of at least one access right of this transaction.
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公开(公告)号：US11829188B2
公开(公告)日：2023-11-28
申请号：US16953993
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Loic Pallardy , Nicolas Anquet , Dragos Davidescu
CPC classification number: G06F11/0751 , G06F11/0721 , G06F11/3656 , G06F13/4282 , G06F21/44 , G06F2213/0016 , G06F2213/0038
Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
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公开(公告)号：US20170220443A1
公开(公告)日：2017-08-03
申请号：US15253002
申请日：2016-08-31
Applicant: STMicroelectronics (Alps) SAS
Inventor： Mickael Broutin , Benoit Lelievre , Nicolas Anquet
CPC classification number: G06F11/27 , G06F11/0778 , G11C7/24 , G11C29/12 , G11C2029/3602
Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.
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公开(公告)号：US11962462B2
公开(公告)日：2024-04-16
申请号：US18321516
申请日：2023-05-22
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L41/0803 , G06F15/173 , G06F15/177 , H04L41/0813 , H04L49/109 , G06F21/85
CPC classification number: H04L41/0813 , G06F15/17306 , G06F15/177 , H04L41/0803 , H04L49/109 , G06F21/85
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20210160193A1
公开(公告)日：2021-05-27
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L12/933 , H04L12/24
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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Patent Agency Ranking
公开(公告)号：US10331530B2
公开(公告)日：2019-06-25
申请号：US15253002
申请日：2016-08-31
Applicant: STMicroelectronics (Alps) SAS
Inventor： Mickael Broutin , Benoit Lelievre , Nicolas Anquet
Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.
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公开(公告)号：US12045378B2
公开(公告)日：2024-07-23
申请号：US17657212
申请日：2022-03-30
Inventor： Franck Albesa , Nicolas Anquet
CPC classification number: G06F21/79 , G06F21/602 , H04L9/0894 , H04L9/14
Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
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公开(公告)号：US12045377B2
公开(公告)日：2024-07-23
申请号：US17657020
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/32 , G06F9/4401 , G06F21/72 , H04L9/08
CPC classification number: G06F21/72 , G06F9/4401 , H04L9/0861
Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
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公开(公告)号：US20220318439A1
公开(公告)日：2022-10-06
申请号：US17657212
申请日：2022-03-30
Inventor： Franck Albesa , Nicolas Anquet
Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
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公开(公告)号：US20220318434A1
公开(公告)日：2022-10-06
申请号：US17657020
申请日：2022-03-29
Inventor： Franck Albesa , Nicolas Anquet
IPC: G06F21/72 , H04L9/08 , G06F9/4401
Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
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