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公开(公告)号：US20230238060A1
公开(公告)日：2023-07-27
申请号：US18158232
申请日：2023-01-23
Inventor： Antonino CONTE , Francesco LA ROSA
CPC classification number: G11C13/0004 , G11C13/0069 , G11C13/004 , H01L23/576
Abstract: Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
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公开(公告)号：US20170084749A1
公开(公告)日：2017-03-23
申请号：US15365768
申请日：2016-11-30
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Marc MANTELLI , Stephan NIEL , Arnaud REGNIER , Francesco LA ROSA , Julien DELALLEAU
IPC: H01L29/788 , G11C16/04 , H01L27/115 , H01L21/28 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7883 , G11C16/0425 , G11C16/14 , H01L21/266 , H01L21/28273 , H01L21/30604 , H01L21/308 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L29/42328 , H01L29/42336 , H01L29/66666 , H01L29/66825 , H01L29/788
Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
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公开(公告)号：US20210319836A1
公开(公告)日：2021-10-14
申请号：US17224024
申请日：2021-04-06
Inventor： Francesco LA ROSA , Enrico CASTALDO , Francesca GRANDE , Santi Nunzio Antonino PAGANO , Giuseppe NASTASI , Franco ITALIANO
IPC: G11C16/34 , G11C16/14 , G11C16/10 , G11C16/26 , H01L27/11529
Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
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公开(公告)号：US20190123737A1
公开(公告)日：2019-04-25
申请号：US16161533
申请日：2018-10-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy FORT , Nicolas BORREL , Francesco LA ROSA
IPC: H03K17/22 , G01R19/165 , H03K5/24 , G05F3/26 , G06F1/28
Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
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公开(公告)号：US20160308011A1
公开(公告)日：2016-10-20
申请号：US15195784
申请日：2016-06-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco LA ROSA , Stephan NIEL , Julien DELALLEAU , Arnaud REGNIER
IPC: H01L29/423 , H01L27/115 , H01L29/66 , H01L21/28 , H01L21/306 , H01L29/788 , G11C16/14
CPC classification number: H01L29/42328 , G11C16/0425 , G11C16/14 , H01L21/28273 , H01L21/30604 , H01L21/32051 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L29/42336 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/788 , H01L29/7881 , H01L29/7883 , H01L29/7885
Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
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Patent Agency Ranking
公开(公告)号：US20160049179A1
公开(公告)日：2016-02-18
申请号：US14751701
申请日：2015-06-26
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Francesco LA ROSA
Abstract: A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.
Abstract translation: 读出放大器包括：两个检测输入端，一个锁存电路，包括彼此耦合的两个部分，并且各自提供一个数据信号。 每个部分分别由P沟道控制晶体管供电，其具有接收与两个检测输入的相应检测输入链接的控制信号的栅极端子。 读出放大器包括控制电路，其被配置为当控制信号达到参考电压时，将每个控制信号减小到足够低的电压以将相应的控制晶体管置于导通状态。 当对应的一个控制晶体管处于导通状态时，锁存电路被激活以提供其中一个数据信号。
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7.发明申请公开(公告)号：US20150236031A1
公开(公告)日：2015-08-20
申请号：US14625356
申请日：2015-02-18
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Marc MANTELLI , Stephan NIEL , Arnaud REGNIER , Francesco LA ROSA , Julien DELALLEAU
IPC: H01L27/115 , H01L29/788 , G11C16/14 , H01L21/3213 , H01L21/306 , H01L21/308 , H01L21/266 , H01L29/423 , H01L21/28
CPC classification number: H01L29/7883 , G11C16/0425 , G11C16/14 , H01L21/266 , H01L21/28273 , H01L21/30604 , H01L21/308 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L27/11553 , H01L27/11556 , H01L29/42328 , H01L29/42336 , H01L29/66666 , H01L29/66825 , H01L29/788
Abstract: The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
Abstract translation: 本公开涉及一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸到垂直选择栅极的一部分上方，存储器单元包括 注入在与选择栅极相对延伸的垂直沟道区域的相交处的掺杂区域和与浮动栅极相对延伸的水平沟道区域。
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公开(公告)号：US20200342930A1
公开(公告)日：2020-10-29
申请号：US16853036
申请日：2020-04-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco LA ROSA
IPC: G11C11/4094 , G11C11/4099 , G11C11/4091 , G11C11/408 , G11C5/02
Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.
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公开(公告)号：US20190123736A1
公开(公告)日：2019-04-25
申请号：US16161531
申请日：2018-10-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas BORREL , Jimmy FORT , Francesco LA ROSA
Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
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公开(公告)号：US20180197963A1
公开(公告)日：2018-07-12
申请号：US15914846
申请日：2018-03-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francesco LA ROSA , Stephan NIEL , Arnaud REGNIER , Julien DELALLEAU
IPC: H01L29/423 , H01L29/788 , G11C16/04 , H01L29/78 , H01L29/66 , H01L27/11524 , H01L27/11521 , H01L21/3213 , H01L21/3205 , H01L21/306 , H01L21/28 , G11C16/14
CPC classification number: H01L29/42328 , G11C16/0425 , G11C16/14 , H01L21/30604 , H01L21/32051 , H01L21/32133 , H01L27/11521 , H01L27/11524 , H01L29/40114 , H01L29/42336 , H01L29/66666 , H01L29/66825 , H01L29/7827 , H01L29/788 , H01L29/7881 , H01L29/7883 , H01L29/7885
Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
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