公开(公告)号：US20190102328A1

公开(公告)日：2019-04-04

申请号：US16148761

申请日：2018-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: G06F13/16 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G06F13/42

Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.

公开(公告)号：US20240304237A1

公开(公告)日：2024-09-12

申请号：US18583574

申请日：2024-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Christophe GONCALVES ,  Marc BATTISTA ,  Francois TAILLIET

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

Abstract: The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.

公开(公告)号：US20240087652A1

公开(公告)日：2024-03-14

申请号：US18243193

申请日：2023-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/16

Abstract: A nonvolatile memory device has a “split-voltage” architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors for memory cells of a memory word are gate controlled by a control element. All control elements of a same row are controlled by a first control signal generated by a first row control circuit in response to a set-reset (SR) latch output signal output for a selected row. In order to write a piece of data in a memory word, the first row control circuit confers onto the first control signal an erasing voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal without modifying, between erasing and programming the memory word, the state of the latch output signal for the selected row.

公开(公告)号：US20200035293A1

公开(公告)日：2020-01-30

申请号：US16043497

申请日：2018-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Marc BATTISTA

IPC: G11C11/419 ,  G11C11/4096 ,  G11C11/418 ,  G11C8/12 ,  G11C7/22

Abstract: Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

公开(公告)号：US20240304224A1

公开(公告)日：2024-09-12

申请号：US18583568

申请日：2024-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Christophe GONCALVES ,  Marc BATTISTA ,  Francois TAILLIET

IPC: G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/1048 ,  G11C7/1069

Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.

公开(公告)号：US20200265894A1

公开(公告)日：2020-08-20

申请号：US16866955

申请日：2020-05-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA

IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11517

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US20200035303A1

公开(公告)日：2020-01-30

申请号：US16043425

申请日：2018-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Marc BATTISTA

IPC: G11C14/00 ,  G11C8/10 ,  G11C7/06 ,  G11C11/419

Abstract: Disclosed herein is a method of operating a non-volatile static random access NVSRAM memory formed from words. Each word includes NVSRAM cells, each of those NVSRAM cells having an SRAM cell and an electronically erasable programmable read only memory EEPROM cell. If the SRAM cells of a word have been accessed since powerup, data is read from the NVSRAM cells of that word through the SRAM cells. However, if the SRAM cells of that word have not been written since powerup, data is read from the NVSRAM cells of that word through the EEPROM cells.

公开(公告)号：US20220406668A1

公开(公告)日：2022-12-22

申请号：US17839976

申请日：2022-06-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: H01L21/66 ,  H01L23/58 ,  H01L23/00

Abstract: An electronic chip includes a seal ring whose shape is contained within a rectangle, of a width equal to a maximum width of the electronic chip and a length equal to a maximum length of the electronic chip. At least one test pad is arranged at least partially within the rectangle. The test pad is shared with at least one other adjacent electronic chip.

公开(公告)号：US20220367497A1

公开(公告)日：2022-11-17

申请号：US17734963

申请日：2022-05-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA ,  Philippe BOIVIN

IPC: H01L27/11529 ,  H01L27/11524

Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.

公开(公告)号：US20200373295A1

公开(公告)日：2020-11-26

申请号：US16877935

申请日：2020-05-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: H01L27/02 ,  H01L23/50

Abstract: A first power supply rail is provided as a power supply tree configured with couplings to distribute a supply voltage to active elements of the circuit. A second power supply rail is provided as an electrostatic discharge channel and is not configured with distribution tree couplings to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power supply rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects another end of the second power supply rail to the first power supply rail at the second electrostatic discharge circuit.