公开(公告)号：US10714583B2

公开(公告)日：2020-07-14

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara ,  Julien Delalleau

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/8234

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US10211291B2

公开(公告)日：2019-02-19

申请号：US15864451

申请日：2018-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US10177101B2

公开(公告)日：2019-01-08

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L23/58 ,  H01L21/768

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US20170373001A1

公开(公告)日：2017-12-28

申请号：US15380894

申请日：2016-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L22/22 ,  H01L22/32 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/60

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US10043741B2

公开(公告)日：2018-08-07

申请号：US15380894

申请日：2016-12-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: G01R31/26 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L21/66

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US20180145040A1

公开(公告)日：2018-05-24

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/573 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L27/088

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US09899476B2

公开(公告)日：2018-02-20

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06 ,  H01L29/78 ,  H01L27/112

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20150340426A1

公开(公告)日：2015-11-26

申请号：US14715814

申请日：2015-05-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Sylvie Wuidart ,  Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/423 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42356 ,  H01L29/66181 ,  H01L29/7842 ,  H01L29/94 ,  H01L29/945

Abstract: An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.

Abstract translation: 集成电路包括基板和至少部分地设置在由绝缘区域限制的基板的有源区域内的电路部件（诸如MOS器件或电阻）。 结合绝缘区域提供包括第一电极（用于连接到第一电位例如接地）和第二电极（用于连接到第二电位例如电源电压）的电容结构。 第一和第二电极之一至少部分地位于绝缘区域内。 因此，电容结构被配置为允许有效区域内的压缩应力的降低。

公开(公告)号：US12087683B2

公开(公告)日：2024-09-10

申请号：US17566437

申请日：2021-12-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L22/20 ,  H01L22/22 ,  H01L22/32 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/60 ,  H01L22/14

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

公开(公告)号：US11244893B2

公开(公告)日：2022-02-08

申请号：US16033109

申请日：2018-07-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet ,  Guilhem Bouton

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02

Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.