公开(公告)号：US20130057334A1

公开(公告)日：2013-03-07

申请号：US13669259

申请日：2012-11-05

Applicant: STMicroelectronics SA ,  ST Ericsson SA

Inventor： Frederic Hasbani ,  Pascal Urard ,  Fabrice Blisson ,  David Jacquet

IPC: H03K3/00

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。

公开(公告)号：US10585143B2

公开(公告)日：2020-03-10

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal Urard ,  Florian Cacho ,  Vincent Huard ,  Alok Kumar Tripathi

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181 ,  G06F17/50

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US10263603B2

公开(公告)日：2019-04-16

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/00 ,  H03K3/0233 ,  H03K3/3562

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US20180083603A1

公开(公告)日：2018-03-22

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/356 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/02335 ,  H03K3/35625 ,  H03K19/0002

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US09557805B2

公开(公告)日：2017-01-31

申请号：US14279514

申请日：2014-05-16

Applicant: STMicroelectronics SA

Inventor： Fabien Todeschini ,  Christophe Planat ,  Patrizia Milazzo ,  Salvatore Tricomi ,  Séverin Trochut ,  Pascal Urard

IPC: G06F1/32 ,  H02J7/35

CPC classification number: G06F1/3293 ,  H02J7/35

Abstract: A power management circuit including, between a first terminal intended to be connected to an electric power generation source and a second terminal intended to be connected to a load to be powered, a linear regulator and a circuit capable of activating the linear regulator when the power supplied by said source is greater than a first threshold.

Abstract translation: 一种电力管理电路，包括在要连接到发电源的第一端子和旨在连接到要供电的负载的第二端子之间，线性调节器和能够在所述电力的情况下启动所述线性调节器的电路 由所述源提供的大于第一阈值。

公开(公告)号：US08994416B2

公开(公告)日：2015-03-31

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03B19/00 ,  H03K3/02 ,  H03K3/037

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20140232575A1

公开(公告)日：2014-08-21

申请号：US14179993

申请日：2014-02-13

Applicant: STMICROELECTRONICS SA

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault

IPC: H03M1/06

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.

Abstract translation: 根据一种实施方式，一种方法包括估计，其一方面包括涉及采样信号的至少一部分的相关处理，从代表时间导数的导出信号中收集的至少一个第一信号的至少一部分 的采样信号和N个部分滤波信号的至少一部分，分别代表在采样信号侧翼的N对包围版本之间的N个加权差，N大于或等于1.另一方面，估计包括矩阵 对该相关处理的结果进行处理。 M-1列车的校正处理涉及从派生信号和一组M-1移位系数收集的M-1个第二信号。

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US20180083602A1

公开(公告)日：2018-03-22

申请号：US15460520

申请日：2017-03-16

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Pascal Urard

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/35625 ,  H03K19/0002

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

公开(公告)号：US20130157562A1

公开(公告)日：2013-06-20

申请号：US13714151

申请日：2012-12-13

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pascal Urard ,  Christophe Regnier ,  Daniel Gloria ,  Olivier Hinsinger ,  Philippe Cavenel ,  Lionel Balme

IPC: H04B7/24

CPC classification number: H04B5/0031 ,  G06F1/1694 ,  G06F1/1698 ,  G06F3/017 ,  G06F21/35 ,  H04B7/24 ,  H04L63/0869 ,  H04L63/18 ,  H04W4/008 ,  H04W4/80 ,  H04W12/06 ,  H04W12/08

Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.

Abstract translation: 无线单元包括第一运动敏感设备; 用于与另一无线单元无线通信的通信电路; 以及处理装置，被配置为将从所述第一运动敏感装置接收的至少一个第一运动矢量与从所述另一无线单元的第二运动敏感装置接收的至少一个第二运动矢量进行比较。