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公开(公告)号：US20130157562A1
公开(公告)日：2013-06-20
申请号：US13714151
申请日：2012-12-13
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Pascal Urard , Christophe Regnier , Daniel Gloria , Olivier Hinsinger , Philippe Cavenel , Lionel Balme
IPC: H04B7/24
CPC classification number: H04B5/0031 , G06F1/1694 , G06F1/1698 , G06F3/017 , G06F21/35 , H04B7/24 , H04L63/0869 , H04L63/18 , H04W4/008 , H04W4/80 , H04W12/06 , H04W12/08
Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.
Abstract translation: 无线单元包括第一运动敏感设备; 用于与另一无线单元无线通信的通信电路; 以及处理装置，被配置为将从所述第一运动敏感装置接收的至少一个第一运动矢量与从所述另一无线单元的第二运动敏感装置接收的至少一个第二运动矢量进行比较。
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公开(公告)号：US09647724B2
公开(公告)日：2017-05-09
申请号：US13714151
申请日：2012-12-13
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Pascal Urard , Christophe Regnier , Daniel Gloria , Olivier Hinsinger , Philippe Cavenel , Lionel Balme
CPC classification number: H04B5/0031 , G06F1/1694 , G06F1/1698 , G06F3/017 , G06F21/35 , H04B7/24 , H04L63/0869 , H04L63/18 , H04W4/008 , H04W4/80 , H04W12/06 , H04W12/08
Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.
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公开(公告)号：US12232435B2
公开(公告)日：2025-02-18
申请号：US18130184
申请日：2023-04-03
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
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公开(公告)号：US10797234B2
公开(公告)日：2020-10-06
申请号：US16182990
申请日：2018-11-07
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Olivier Hinsinger
Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
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公开(公告)号：US10304893B2
公开(公告)日：2019-05-28
申请号：US15592437
申请日：2017-05-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Daniel Benoit , Olivier Hinsinger , Emmanuel Gourvest
IPC: H01L27/146
Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
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Patent Agency Ranking
公开(公告)号：US20180102385A1
公开(公告)日：2018-04-12
申请号：US15592437
申请日：2017-05-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Daniel Benoit , Olivier Hinsinger , Emmanuel Gourvest
IPC: H01L27/146
CPC classification number: H01L27/1464 , H01L27/14609 , H01L27/1462 , H01L27/14623 , H01L27/14629 , H01L27/1463 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L27/14698
Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
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公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
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公开(公告)号：US11329225B2
公开(公告)日：2022-05-10
申请号：US17012558
申请日：2020-09-04
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Olivier Hinsinger
Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
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9.发明授权公开(公告)号：US11908809B2
公开(公告)日：2024-02-20
申请号：US17325999
申请日：2021-05-20
Inventor： Eric Sabouret , Krysten Rochereau , Olivier Hinsinger , Flore Persin-Crelerot
IPC: H01L23/00 , H05K3/34 , H01L23/498 , H01L21/66
CPC classification number: H01L23/562 , H01L22/34 , H01L23/49816 , H01L24/05 , H05K3/3436 , H01L2224/05093 , H01L2924/14
Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
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10.发明授权公开(公告)号：US11018096B2
公开(公告)日：2021-05-25
申请号：US16210149
申请日：2018-12-05
Inventor： Eric Sabouret , Krysten Rochereau , Olivier Hinsinger , Flore Persin-Crelerot
IPC: H01L21/66 , H01L23/00 , H05K3/34 , H01L23/498
Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
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