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1.发明申请ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING 有权适用于高性能误差计算的自适应多级滑块公开(公告)号：US20140035644A1
公开(公告)日：2014-02-06
申请号：US14045642
申请日：2013-10-03
Inventor： Chittoor PARTHASARATHY , Nitin CHAWLA , Kallol CHATTERJEE , Pascal URARD
IPC: H03K3/02
CPC classification number: H03K3/02 , H03K3/0375
Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。
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公开(公告)号：US20220209777A1
公开(公告)日：2022-06-30
申请号：US17521210
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Gagan MIDHA , Kallol CHATTERJEE , Anand KUMAR , Ankit GUPTA
Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.
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公开(公告)号：US20220196485A1
公开(公告)日：2022-06-23
申请号：US17521123
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Pijush Kanti PANJA , Kallol CHATTERJEE , Atul DWIVEDI
Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ΔVbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ΔVbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.
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公开(公告)号：US20210265947A1
公开(公告)日：2021-08-26
申请号：US17175732
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： Gagan MIDHA , Anurup MITRA , Kallol CHATTERJEE
Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
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公开(公告)号：US20210135681A1
公开(公告)日：2021-05-06
申请号：US17089090
申请日：2020-11-04
Applicant: STMicroelectronics International N.V.
Inventor： Gagan MIDHA , Kallol CHATTERJEE
Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
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Patent Agency Ranking
公开(公告)号：US20230412155A1
公开(公告)日：2023-12-21
申请号：US18323998
申请日：2023-05-25
Applicant: STMicroelectronics International N.V.
Inventor： Nitin JAIN , Anand KUMAR , Kallol CHATTERJEE
CPC classification number: H03K3/0307 , H03K3/3545 , H03K3/012
Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.
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公开(公告)号：US20230231559A1
公开(公告)日：2023-07-20
申请号：US18151337
申请日：2023-01-06
Applicant: STMicroelectronics International N.V.
Inventor： Kallol CHATTERJEE , Rohit Kumar GUPTA
IPC: H03K19/0185
CPC classification number: H03K19/018521
Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.
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公开(公告)号：US20150002197A1
公开(公告)日：2015-01-01
申请号：US14046041
申请日：2013-10-04
Inventor： Kallol CHATTERJEE , Nitin AGARWAL , Junaid YOUSUF , Nitin GUPTA , Pierre DAUTRICHE
IPC: H03L7/095
CPC classification number: H03L7/095
Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.
Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。
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公开(公告)号：US20220352896A1
公开(公告)日：2022-11-03
申请号：US17863708
申请日：2022-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan MIDHA , Kallol CHATTERJEE , Anand KUMAR , Ankit GUPTA
Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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公开(公告)号：US20200014387A1
公开(公告)日：2020-01-09
申请号：US16503960
申请日：2019-07-05
Applicant: STMicroelectronics International N.V.
Inventor： Atul DWIVEDI , Paras GARG , Kallol CHATTERJEE
IPC: H03K19/0185 , G01R31/317
Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.
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