公开(公告)号：US20240321774A1

公开(公告)日：2024-09-26

申请号：US18399519

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Chiwan Song ,  Seonkyu Kim ,  Hyunna Bae ,  Seungmin Baek ,  Yongjae Song ,  Joonseok Oh ,  Jaewook Jung ,  Seokil Hong

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/31 ,  H01L23/492 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/32055 ,  H01L23/3135 ,  H01L23/4926 ,  H01L24/48 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.

公开(公告)号：US20240258242A1

公开(公告)日：2024-08-01

申请号：US18421284

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Chiwan Song ,  Seungmin Baek ,  Joohyung Lee ,  Joonseok Oh ,  Junghyun Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/20 ,  H01L25/105 ,  H01L25/18 ,  H10B80/00 ,  H01L24/19 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2924/01028 ,  H01L2924/01029

Abstract: A semiconductor package includes a package body, a fan-in-chip structure (FICS) in the package body, a first redistribution structure, and a second redistribution structure. The FICS includes a first chip having a front surface and a rear surface, a bridge wiring structure including a bridge wiring layer on the rear surface of the first chip, and a bridge pad electrically connected to the bridge wiring layer. The first redistribution structure is on a bottom surface of the package body and the front surface of the first chip and includes a first redistribution element. The second redistribution structure is on a top surface of the package body and the rear surface of the first chip and includes a second redistribution element electrically connected to the bridge wiring structure.