公开(公告)号：US20240355709A1

公开(公告)日：2024-10-24

申请号：US18637022

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Seonkyu Kim ,  Seungmin Baek ,  Joonseok Oh ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1815

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, and a first fillet layer between the base chip and the first semiconductor chip. The base chip includes a base substrate, a plurality of through-electrodes penetrating through the base substrate, a protective layer surrounding the plurality of through-electrodes and covering an upper surface of the base substrate, and a plurality of trenches vertically penetrating the protective layer. The plurality of through-electrodes form a transistor area on the base substrate, and the plurality of trenches include first trenches disposed between adjacent through-vias in the transistor area and second trenches disposed in an outer side portion of the transistor area.

公开(公告)号：US11935858B2

公开(公告)日：2024-03-19

申请号：US17077646

申请日：2020-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Baek

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0133 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.

公开(公告)号：US20240194627A1

公开(公告)日：2024-06-13

申请号：US18584488

申请日：2024-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Baek

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0133 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19107

Abstract: A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.

公开(公告)号：US20240162130A1

公开(公告)日：2024-05-16

申请号：US18223757

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Seungmin Baek ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827

Abstract: A semiconductor package includes a first redistribution wiring layer having first and second surfaces opposite to each other, the first redistribution wiring layer including a plurality of first redistribution wires and a plurality of landing pads electrically connected to the first redistribution wires, the plurality of landing pads exposed from the second surface, a second redistribution wiring layer disposed on the first surface of the first redistribution wiring layer, the second redistribution wiring layer including an insulating layer, a logic semiconductor chip provided in the insulating layer, second redistribution wires electrically connected to the logic semiconductor chip, and third redistribution wires electrically connected to the first redistribution wires, the third redistribution wires extending to penetrate the insulating layer, a third redistribution wiring layer disposed on the second redistribution wiring layer, the third redistribution wiring layer including fourth redistribution wires electrically connected to the third redistribution wires, and a semiconductor substrate disposed on an upper surface of the third redistribution wire layer, the semiconductor substrate including at least one memory semiconductor chip electrically connected to the fourth redistribution wires.

公开(公告)号：US20240258242A1

公开(公告)日：2024-08-01

申请号：US18421284

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Chiwan Song ,  Seungmin Baek ,  Joohyung Lee ,  Joonseok Oh ,  Junghyun Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/20 ,  H01L25/105 ,  H01L25/18 ,  H10B80/00 ,  H01L24/19 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2924/01028 ,  H01L2924/01029

Abstract: A semiconductor package includes a package body, a fan-in-chip structure (FICS) in the package body, a first redistribution structure, and a second redistribution structure. The FICS includes a first chip having a front surface and a rear surface, a bridge wiring structure including a bridge wiring layer on the rear surface of the first chip, and a bridge pad electrically connected to the bridge wiring layer. The first redistribution structure is on a bottom surface of the package body and the front surface of the first chip and includes a first redistribution element. The second redistribution structure is on a top surface of the package body and the rear surface of the first chip and includes a second redistribution element electrically connected to the bridge wiring structure.

公开(公告)号：US20240321774A1

公开(公告)日：2024-09-26

申请号：US18399519

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Chiwan Song ,  Seonkyu Kim ,  Hyunna Bae ,  Seungmin Baek ,  Yongjae Song ,  Joonseok Oh ,  Jaewook Jung ,  Seokil Hong

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/31 ,  H01L23/492 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/32055 ,  H01L23/3135 ,  H01L23/4926 ,  H01L24/48 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.