公开(公告)号：US12288578B2

公开(公告)日：2025-04-29

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Byeonggyu Park ,  Yeonggeol Song

IPC: G11C11/406 ,  G11C11/4093

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US10903884B2

公开(公告)日：2021-01-26

申请号：US16727391

申请日：2019-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seijoon Shim ,  Joonho Cho ,  Hayoung Yang ,  Eunae Lee ,  Taejun Jang ,  Jonghwan Kim

IPC: H04L1/02 ,  H04B7/06 ,  H04L5/00 ,  H04L27/26 ,  H04B7/0417 ,  H04B7/08

Abstract: A base station for transmitting and receiving signals in a wireless communication system is provided. The base station includes a transceiver, and at least one processor configured to obtain reception antenna weights for the base station including an array of a plurality of antennas, and transmission antenna weights for at least one user equipment (UE), convert signals received from the at least one UE through a plurality of reception paths, into beam-domain signals, based on the transmission antenna weights and the reception antenna weights, combine the converted beam-domain signals by applying predefined combining weights to the converted beam-domain signals, and obtain data from the combined signals.

公开(公告)号：USD819002S1

公开(公告)日：2018-05-29

申请号：US29598849

申请日：2017-03-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Eunae Lee ,  Jihee Kwak

公开(公告)号：US20240096391A1

公开(公告)日：2024-03-21

申请号：US18341128

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Myungkyu Lee

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

公开(公告)号：US20230260562A1

公开(公告)日：2023-08-17

申请号：US18138849

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/12

CPC classification number: G11C11/406 ,  G11C11/4091 ,  G11C11/4087 ,  G11C11/40622 ,  G11C11/40611 ,  G11C7/12 ,  G11C11/4085 ,  G11C7/1078

Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

公开(公告)号：USD895591S1

公开(公告)日：2020-09-08

申请号：US29680815

申请日：2019-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Eunae Lee ,  Jihee Kwak ,  Soyoon Jeon ,  Moonjung Jang ,  Jihyun Moon

公开(公告)号：USD883964S1

公开(公告)日：2020-05-12

申请号：US29640585

申请日：2018-03-15

Applicant: Samsung Electronics Co., Ltd.

Designer： Moonjung Jang ,  Jiyun Lim ,  Jihee Kwak ,  Jihyun Moon ,  Eunae Lee ,  Soyoon Jeon

公开(公告)号：USD876411S1

公开(公告)日：2020-02-25

申请号：US29640602

申请日：2018-03-15

Applicant: Samsung Electronics Co., Ltd.

Designer： Jiyun Lim ,  Jihee Kwak ,  Jihyun Moon ,  Eunae Lee ,  Moonjung Jang ,  Soyoon Jeon

公开(公告)号：US12020739B2

公开(公告)日：2024-06-25

申请号：US18138849

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

IPC: G11C7/12 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10 ,  G11C8/10

CPC classification number: G11C11/406 ,  G11C7/12 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C7/1078 ,  G11C8/10

Abstract: A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

公开(公告)号：US11551775B2

公开(公告)日：2023-01-10

申请号：US17313236

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggi Ahn ,  Yesin Ryu ,  Jun Jin Kong ,  Eunae Lee ,  Jihyun Choi

IPC: G11C29/14 ,  G11C29/42 ,  G11C29/46 ,  G11C29/52 ,  G11C29/12

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.