公开(公告)号：US20240179917A1

公开(公告)日：2024-05-30

申请号：US18360128

申请日：2023-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minji PARK ,  Dongha SHIN ,  Hongsoo JEON

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

Abstract: Disclosed are semiconductor memory devices comprising a peripheral region including a substrate, high voltage transistors on the substrate, first lower lines connected to the high voltage transistors, and second lower lines connected to the first lower lines, and a cell region on the peripheral region. The first and the second lower lines extend along a first direction parallel to an upper surface of the substrate. The first lower lines include first high voltage lines and first low voltage lines. The second lower lines include second high voltage lines and second low voltage lines. The second high voltage lines and the first low voltage lines separated in a second direction parallel to the upper surface of the substrate and a third direction perpendicular to the upper surface of the substrate, and the second low voltage lines and the first high voltage lines separated in the second direction and the third direction.

公开(公告)号：US20230080436A1

公开(公告)日：2023-03-16

申请号：US17704701

申请日：2022-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Ho YU ,  Hongsoo JEON

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes; a first transistor on a substrate and including a first gate electrode, a second transistor on the substrate and including a second gate electrode adjacent to the first gate electrode, an electrode structure including electrodes vertically stacked on the first and second transistors and including first and second pads adjacent to in the first direction, first and second landing pads between the substrate and the electrode structure connected respectively to the first and second landing pads, a first penetration electrode penetrating the electrode structure to connect the first landing pad and the first pad, a second penetration electrode penetrating the electrode structure to connect the second landing pad and the second pad, and lower interconnection lines between the first landing pad and the second landing pad and extending in a second direction substantially perpendicular to the first direction.

公开(公告)号：US20220122651A1

公开(公告)日：2022-04-21

申请号：US17322065

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjee KIM ,  Seungyeon KIM ,  Sangwan NAM ,  Hongsoo JEON ,  Jiho CHO

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4099 ,  G11C5/06

Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

公开(公告)号：US20230140959A1

公开(公告)日：2023-05-11

申请号：US18149206

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk Yu

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L24/05 ,  H01L24/08 ,  G11C16/08 ,  G11C16/0483 ,  H01L2924/14511 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US20210202457A1

公开(公告)日：2021-07-01

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk YU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.