公开(公告)号：US20190158320A1

公开(公告)日：2019-05-23

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: H04L25/02 ,  G11C13/00 ,  G11C11/16 ,  G11C16/26

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US20180337663A1

公开(公告)日：2018-11-22

申请号：US15844172

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Younghun Seo

IPC: H03K5/08 ,  G05F1/46 ,  H03K5/24

CPC classification number: H03K5/08 ,  G05F1/46 ,  H03K5/24

Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.

公开(公告)号：US10734043B2

公开(公告)日：2020-08-04

申请号：US16054633

申请日：2018-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ju Kim ,  Dong-Seok Kang ,  Hye Jung Kwon ,  Byungchul Kim ,  Seungjun Bae

IPC: G11C8/00 ,  G11C7/10 ,  H03L7/08 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/22 ,  G11C7/02 ,  G06F13/42 ,  G11C11/4093 ,  G06F13/16

Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

公开(公告)号：US10666467B2

公开(公告)日：2020-05-26

申请号：US16108894

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Seungjun Bae ,  Yongjae Lee ,  Young-Sik Kim ,  Young-Ju Kim ,  Suyeon Doo ,  Yoon-Joo Eom

IPC: G11C7/10 ,  H04L25/02 ,  G11C13/00 ,  G11C16/26 ,  G11C11/16

Abstract: A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

公开(公告)号：US12154616B2

公开(公告)日：2024-11-26

申请号：US18493051

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C7/14 ,  G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US11862234B2

公开(公告)日：2024-01-02

申请号：US17457077

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C7/20 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C11/4093 ,  G11C5/147 ,  G11C7/02 ,  G11C7/1069 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/028 ,  G11C29/50 ,  G11C29/021 ,  G11C29/023 ,  G11C2207/2254

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US11195571B2

公开(公告)日：2021-12-07

申请号：US16136895

申请日：2018-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Joo Eom ,  Seungjun Bae ,  Hye Jung Kwon ,  Young-Ju Kim

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/20 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US10969420B2

公开(公告)日：2021-04-06

申请号：US16023736

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Jung Kwon ,  Seungjun Bae

IPC: G01R31/02 ,  G01R31/26 ,  H03K3/03 ,  G01R31/317 ,  G01R31/28 ,  H01L21/66

Abstract: A test circuit includes a first logic gate that receives a test signal or a first voltage, a second logic gate that receives the test signal, a third logic gate that receives an output of the first logic gate, an output of the second logic gate, or a second voltage, a fourth logic gate that receives the output of the first logic gate or the output of the second logic gate, and a power circuit that prevents the second and fourth logic gates from being driven by supplying power to the second and fourth logic gates when the first logic gate receives the first voltage and the third logic gate receives the second voltage.

公开(公告)号：US10305457B2

公开(公告)日：2019-05-28

申请号：US15844172

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye Jung Kwon ,  Younghun Seo

IPC: H03L5/00 ,  H03K5/08 ,  H03K5/24 ,  G05F1/46 ,  G05F1/575

Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.