公开(公告)号：US20190130953A1

公开(公告)日：2019-05-02

申请号：US15997964

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun LEE ,  Joon Soo KWON ,  Byung Soo KIM ,  Su-Yong KIM ,  Sang-Soo PARK ,  Il Han PARK ,  Kang-Bin LEE ,  Jong-Hoon LEE ,  Na-Young CHOI

IPC: G11C8/08 ,  G06F3/06 ,  G11C16/12 ,  G11C5/14 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

公开(公告)号：US20230410900A1

公开(公告)日：2023-12-21

申请号：US18238212

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G06F11/07

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C16/0483 ,  G06F11/0793 ,  G11C16/10

Abstract: A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US20230144659A1

公开(公告)日：2023-05-11

申请号：US17854163

申请日：2022-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho CHOI ,  Minseok KIM ,  Il Han PARK ,  Jun-Yong PARK ,  Joonsuc JANG

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: Disclosed is a memory device which includes a history table and communicates with a storage controller. A method of operating the memory device includes receiving a first request indicating a first core operation of a first memory block from the storage controller, determining whether history data of the first memory block have a first value or a second value, with reference to the history table, in response to the first request, when it is determined that the history data of the first memory block have the first value, performing the first core operation corresponding to a first type on the first memory block, and after performing the first core operation corresponding to the first type on the first memory block, updating the history data of the first memory block in the history table from the first value to the second value.

公开(公告)号：US20200265908A1

公开(公告)日：2020-08-20

申请号：US16865675

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae BANG ,  Seung Hwan SONG ,  Dae Seok BYEON ,  Il Han PARK ,  Hyun Jun YOON ,  Han Jun LEE ,  Na Young CHOI

IPC: G11C27/00 ,  G11C16/28 ,  G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G06F11/10

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US20180358088A1

公开(公告)日：2018-12-13

申请号：US16108408

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

公开(公告)号：US20130223143A1

公开(公告)日：2013-08-29

申请号：US13721859

申请日：2012-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung CHO ,  Kihwan CHOI ,  Il Han PARK ,  KIiwhan SONG ,  Sangyong YOON

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of programming a nonvolatile memory device comprises determining a temperature condition of the nonvolatile memory device, determining a program pulse period according to the temperature condition, supplying a program voltage to a selected word line using the program pulse period, and supplying a pass voltage to unselected word lines while supplying the program voltage to the selected word line.

Abstract translation: 非易失性存储器件的编程方法包括：确定非易失性存储器件的温度状态，根据温度条件确定编程脉冲周期，使用编程脉冲周期向选定字线提供编程电压，并提供通过电压 在将程序电压提供给所选择的字线的同时，将其作为未选择的字线。

公开(公告)号：US20220415388A1

公开(公告)日：2022-12-29

申请号：US17901308

申请日：2022-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G06F11/07

Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US20170046210A1

公开(公告)日：2017-02-16

申请号：US15155162

申请日：2016-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G06F11/07

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

Abstract translation: 非易失性存储器件的程序验证方法包括执行关于第一级的第一故障位计数操作以产生第一故障位累加值，并将第一故障位累加值和第一故障参考值进行比较以确定程序故障。 当第一故障位累加值小于第一故障参考值时，执行第二级的第二故障位计数操作以产生第二故障位累加值。 将第二故障位累加值与第二参考值进行比较以确定程序故障。 第二个故障参考值与第一个故障参考值不同。