公开(公告)号：US20170308438A1

公开(公告)日：2017-10-26

申请号：US15385124

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-jin YIM ,  Seung-jae LEE ,  Il-han PARK ,  Kang-bin LEE

IPC: G06F11/14 ,  G11C16/26 ,  G11C16/34

CPC classification number: G06F11/1402 ,  G06F2201/805 ,  G06F2201/82 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C16/3495

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a counting circuit configured to obtain a counting result by performing a counting operation on data read from the plurality of memory cells; and a control logic configured to perform a data restoring operation based on the counting result without involvement of a memory controller.

公开(公告)号：US20190164991A1

公开(公告)日：2019-05-30

申请号：US16200714

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon LIM ,  Jin-Young KIM ,  Sang-Won SHIM ,  Il-han PARK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11575 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  G11C16/04

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US20200258911A1

公开(公告)日：2020-08-13

申请号：US16861939

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon LIM ,  Jin-young KIM ,  Sang-won SHIM ,  Il-han PARK

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575 ,  G11C16/08 ,  H01L27/11565 ,  H01L23/522 ,  G11C16/04 ,  H01L23/535 ,  H01L25/18 ,  H01L27/11573

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US20180211715A1

公开(公告)日：2018-07-26

申请号：US15810741

申请日：2017-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-sung CHO ,  Il-han PARK ,  Jung-yun YUN ,  Youn-ho HONG

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3481 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.

公开(公告)号：US20210193680A1

公开(公告)日：2021-06-24

申请号：US17193187

申请日：2021-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon LIM ,  Jin-young KIM ,  Sang-won SHIM ,  Il-han PARK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

公开(公告)号：US20210036015A1

公开(公告)日：2021-02-04

申请号：US17073653

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-soon LIM ,  Jin-young KIM ,  Sang-won SHIM ,  Il-han PARK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell army, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

公开(公告)号：US20190157284A1

公开(公告)日：2019-05-23

申请号：US16193007

申请日：2018-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-hong PARK ,  Bong-soon LIM ,  Il-han PARK

IPC: H01L27/11556 ,  H01L27/06 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/112 ,  H01L27/11582 ,  H01L27/11531 ,  H01L27/11573

Abstract: A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.

公开(公告)号：US20180218775A1

公开(公告)日：2018-08-02

申请号：US15714155

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-hyun KIM ,  Il-han PARK ,  Jong-hoon LEE

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/16 ,  G11C11/56

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459

Abstract: A soft erase method of a memory device including applying a program voltage to a first memory cell in at least one of program loops when a plurality of program loops are performed to program the first memory cell into a Nth programming state, wherein the first memory cell is included in a selected memory cell string connected to a selected first bit line and is connected to a selected word line; and soft erasing a second memory cell by applying, in a first verification interval, a read voltage for verifying a programming state of the first memory cell to the selected word line and applying a first pre-pulse to a gate of a string select transistor of each of a plurality of unselected memory cell strings connected to the first bin line and a plurality of unselected memory cell strings connected to an unselected second bit line.