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    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES
    1.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES 审中-公开
    用于制造具有电极的半导体器件的方法

    公开(公告)号：US20140357077A1

    公开(公告)日：2014-12-04

    申请号：US14190090

    申请日：2014-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SOYOUNG LEE ,  JIN HO AN ,  Byung Lyul PARK ,  JISOON PARK

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/76814 ,  H01L2224/16145

    Abstract: Provided are methods for fabricating semiconductor devices having through electrodes. The method may comprise forming a polishing stop layer having a multi-layered structure on a substrate, forming a via hole partially penetrating the substrate, providing the substrate with a first cleaning solution to first clean the substrate, providing the substrate with a second cleaning solution to second clean the substrate, the second cleaning solution being different from the first cleaning solution, and forming a through electrode in the via hole.

    Abstract translation: 提供了制造具有通孔电极的半导体器件的方法。 该方法可以包括在衬底上形成具有多层结构的抛光停止层，形成部分穿透衬底的通孔，为衬底提供第一清洁溶液以首先清洁衬底，为衬底提供第二清洁溶液 第二清洗溶液与第一清洗溶液不同，在通孔中形成贯通电极。

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220077043A1

    公开(公告)日：2022-03-10

    申请号：US17306988

    申请日：2021-05-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  TEAHWA JEONG ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

    IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

    Abstract: A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.

    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210090984A1

    公开(公告)日：2021-03-25

    申请号：US16830361

    申请日：2020-03-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JINHO CHUN ,  JIN HO AN ,  TEAHWA JEONG ,  JEONGGI JIN ,  JU-IL CHOI ,  ATSUSHI FUJISAKI

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

    Abstract: There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220157702A1

    公开(公告)日：2022-05-19

    申请号：US17381869

    申请日：2021-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

    IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250105116A1

    公开(公告)日：2025-03-27

    申请号：US18974377

    申请日：2024-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JU-IL CHOI ,  GYUHO KANG ,  SEONG-HOON BAE ,  JIN HO AN ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

    Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

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