公开(公告)号：US11836606B2

公开(公告)日：2023-12-05

申请号：US16778168

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Soo Lim ,  Chang Kyu Seol ,  Jae Hun Jang ,  Hye Jeong So ,  Hong Rak Son ,  Pil Sang Yoon

IPC: G06N3/063 ,  G11C11/419 ,  G06F7/544 ,  G06N20/00

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N20/00 ,  G11C11/419

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

公开(公告)号：US11791846B2

公开(公告)日：2023-10-17

申请号：US17314768

申请日：2021-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hun Jang ,  Dong-Min Shin ,  Heon Hwa Cheong ,  Jun Jin Kong ,  Hong Rak Son ,  Se Jin Lim

IPC: H03M13/37 ,  H03M13/03 ,  G06F13/16 ,  G06F11/08 ,  G06F11/10

CPC classification number: H03M13/37 ,  G06F11/085 ,  G06F11/1012 ,  G06F13/1673 ,  H03M13/03

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

公开(公告)号：US20240120019A1

公开(公告)日：2024-04-11

申请号：US18186480

申请日：2023-03-20

Applicant: Samsung Electronics Co, Ltd.

Inventor： Hyeonwu KIM ,  Hojun Jo ,  Jihwan Mun ,  Yoonjin Lee ,  Jae Hun Jang

IPC: G11C29/52 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/102 ,  G11C16/3459

Abstract: Disclosed is a method for programming a storage device including a nonvolatile memory device and a storage controller for storing multi-bit data, programming, by the storage controller, the multi-bit data into the nonvolatile memory device based on a pre-programming operation, reading state group data of the multi-bit data generated in the nonvolatile memory device based on a program result of the pre-programming operation, and performing, by the storage controller, error correction decoding on the state group data.

公开(公告)号：US20210184699A1

公开(公告)日：2021-06-17

申请号：US16917101

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyoul Kwak ,  Jae Hun Jang ,  Hong Rak Son ,  Dong-Min Shin ,  Geunyeong Yu ,  Kangseok Lee ,  Hyunseung Han

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/30 ,  G11C29/42

Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

公开(公告)号：US12282421B2

公开(公告)日：2025-04-22

申请号：US18384646

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyeon Kim ,  Hong Rak Son ,  Jae Hun Jang ,  Mankeun Seo ,  Yong Ho Song

IPC: G06F12/00 ,  G06F12/02

Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

公开(公告)号：US20250112760A1

公开(公告)日：2025-04-03

申请号：US18979286

申请日：2024-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hun Jang ,  Ji Youp Kim ,  Han Byeul Na ,  Young Suk Ra ,  Man Keun Seo ,  Hong Rak Son ,  Se Jin Lim

IPC: H04L9/06 ,  G06F3/06 ,  G06F21/60 ,  G06F21/72

Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.

公开(公告)号：US12019871B2

公开(公告)日：2024-06-25

申请号：US17865621

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk Ra ,  Hanbyeul Na ,  Kwanwoo Noh ,  Mankeun Seo ,  Hong Rak Son ,  Jae Hun Jang

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

公开(公告)号：US11184030B2

公开(公告)日：2021-11-23

申请号：US16917101

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyoul Kwak ,  Jae Hun Jang ,  Hong Rak Son ,  Dong-Min Shin ,  Geunyeong Yu ,  Kangseok Lee ,  Hyunseung Han

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11 ,  G11C29/42 ,  G06F11/30

Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

公开(公告)号：US12200106B2

公开(公告)日：2025-01-14

申请号：US17698639

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hun Jang ,  Ji Youp Kim ,  Han Byeul Na ,  Young Suk Ra ,  Man Keun Seo ,  Hong Rak Son ,  Se Jin Lim

IPC: H04L9/06 ,  G06F3/06 ,  G06F21/60 ,  G06F21/72

Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.

公开(公告)号：US20210132832A1

公开(公告)日：2021-05-06

申请号：US16828170

申请日：2020-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejeong So ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Jinsoo Lim ,  Jae Hun Jang ,  Seonghyeong Choi

IPC: G06F3/06 ,  G06F13/20 ,  G06N3/063 ,  G06N20/00

Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.