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公开(公告)号：US20210265503A1
公开(公告)日：2021-08-26
申请号：US17315818
申请日：2021-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hoon LEE , Gi-gwan PARK , Tae-young KIM
Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
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公开(公告)号：US20170110576A1
公开(公告)日：2017-04-20
申请号：US15290240
申请日：2016-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Soo KIM , Gi-Gwan PARK , Sang-Koo KANG , Koung-Min RYU , Jae-Hoon LEE , Tae-Won HA
IPC: H01L29/78 , H01L29/66 , H01L29/40 , H01L29/423 , H01L29/51
CPC classification number: H01L29/7831 , H01L29/401 , H01L29/42364 , H01L29/513 , H01L29/66484 , H01L29/66545 , H01L29/7843 , H01L29/785 , H01L29/7854
Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
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公开(公告)号：US20140327049A1
公开(公告)日：2014-11-06
申请号：US14338187
申请日：2014-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Hoon LEE , Ki-Se KIM
IPC: H01L23/373 , H01L29/205 , H01L29/20
CPC classification number: H01L23/373 , H01L23/3731 , H01L23/3736 , H01L23/3738 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/872 , H01L2224/13 , H01L2924/12032 , H01L2924/00
Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.
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公开(公告)号：US20130248980A1
公开(公告)日：2013-09-26
申请号：US13775586
申请日：2013-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung-Uk HAN , Jae-Hoon LEE , Jun-Su KIM , Satoru YAMADA , Jin-Seong LEE , Nam-Ho JEON
IPC: H01L27/088
CPC classification number: H01L27/088 , H01L27/108 , H01L27/11
Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.
Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。
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公开(公告)号：US20150162423A1
公开(公告)日：2015-06-11
申请号：US14504847
申请日：2014-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hoon LEE , Tae-Geun KIM , Chan-Ho PARK , Hyun-Jung HER
IPC: H01L29/739 , H01L21/761 , H01L21/265 , H01L29/06 , H01L29/66
CPC classification number: H01L21/761 , H01L21/265 , H01L21/26513 , H01L29/0619 , H01L29/0834 , H01L29/402 , H01L29/4238 , H01L29/66348 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813
Abstract: A semiconductor power device includes a substrate, a plurality of gate electrode structures, a floating well region and a termination ring region. The substrate has a first region and a second region. A plurality of gate electrode structures is formed on the substrate, each of the gate electrode structures extends from the first region to the second region and includes a first gate electrode, a second gate electrode and a connecting portion, the first and second gate electrodes extend in a first direction, and the connecting portion connects end portions of the first and second gate electrodes to each other. The floating well region is doped with impurities between the gate electrode structures in the first region of the substrate, and the floating well region has a first impurity concentration and a first depth. The termination ring region is doped with impurities in the second region of the substrate, is spaced apart from the gate electrode structures, and has a ring shape surrounding the first region, and has the first impurity concentration and the first depth. The semiconductor power device may have a high breakdown voltage.
Abstract translation: 半导体功率器件包括衬底，多个栅电极结构，浮动阱区和端接环区。 衬底具有第一区域和第二区域。 在基板上形成多个栅电极结构，每个栅电极结构从第一区延伸到第二区，并包括第一栅电极，第二栅电极和连接部分，第一和第二栅电极延伸 在第一方向上，连接部将第一和第二栅极的端部彼此连接。 浮置阱区域在衬底的第一区域中的栅电极结构之间掺杂杂质，并且浮置阱区域具有第一杂质浓度和第一深度。 终端环区域在衬底的第二区域中掺杂有杂质，与栅电极结构间隔开，并具有包围第一区域的环状，并且具有第一杂质浓度和第一深度。 半导体功率器件可具有高击穿电压。
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Patent Agency Ranking
公开(公告)号：US20240290888A1
公开(公告)日：2024-08-29
申请号：US18660809
申请日：2024-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hoon LEE , Gi-gwan PARK , Tae-young KIM
CPC classification number: H01L29/7851 , H01L29/0847 , H01L29/155 , H01L29/1608 , H01L29/20 , H01L29/2006 , H01L29/2206 , H01L29/267 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/7854
Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.
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公开(公告)号：US20190088779A1
公开(公告)日：2019-03-21
申请号：US16193521
申请日：2018-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Soo KIM , Gi-Gwan PARK , Sang-Koo KANG , Koung-Min RYU , Jae-Hoon LEE , Tae-Won HA
IPC: H01L29/78 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/66
CPC classification number: H01L29/7831 , H01L29/401 , H01L29/42364 , H01L29/513 , H01L29/66484 , H01L29/66545 , H01L29/7843 , H01L29/785 , H01L29/7854
Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.
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公开(公告)号：US20170005679A1
公开(公告)日：2017-01-05
申请号：US15197073
申请日：2016-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongil YANG , Sang-Hun SIM , Jae-Hoon LEE , Kyu-Han HWANG
CPC classification number: H04B1/18 , H01Q1/241 , H03J5/244 , H04B1/0057 , H04B1/006 , H04B1/0067 , H04B1/1638
Abstract: An electronic device and a receiving method thereof are provided. The electronic device connects at least one filtering module to an antenna. The at least one filtering module filters a wireless signal received from the antenna. The filtering at least one module includes a filter unit. The filter unit includes filters physically coupled to each other, which allows different frequency bands adjacent to each other in the received wireless signal to pass therethrough. An amplifier is connected to the filter unit and amplifies the wireless signal which has passed through the filter unit.
Abstract translation: 提供电子设备及其接收方法。 电子设备将至少一个滤波模块连接到天线。 至少一个滤波模块对从天线接收的无线信号进行滤波。 过滤至少一个模块包括过滤单元。 滤波器单元包括彼此物理耦合的滤波器，其允许接收到的无线信号中彼此相邻的不同频带通过。 放大器连接到滤波器单元并放大已经通过滤波器单元的无线信号。
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公开(公告)号：US20150021658A1
公开(公告)日：2015-01-22
申请号：US14263441
申请日：2014-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Hoon LEE , Tae-Geun KIM , Chan-Ho PARK , Hyun-Jung HER
IPC: H01L27/082 , H01L29/739 , H01L29/10 , H01L29/40
CPC classification number: H01L29/1095 , H01L29/0619 , H01L29/402 , H01L29/407 , H01L29/7397
Abstract: A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width.
Abstract translation: 半导体器件包括发射极和布置在衬底的一个表面上且彼此间隔开的第一场板，设置在衬底的另一个表面上的集电极，设置在衬底中的沟槽栅，场扩散结 设置在所述基板中，以及连接所述沟槽栅极和所述第一场板的第一触点。 第一场板具有相对于第一接触部朝向发射极延伸并且具有第一宽度的第一部分和相对于第一接触部朝向场扩散接合部延伸并具有第二宽度的第二部分。 第二宽度大于第一宽度。
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公开(公告)号：US20170117192A1
公开(公告)日：2017-04-27
申请号：US15215951
申请日：2016-07-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-Ki Min , Gi-Gwan PARK , Sang-Koo KANG , Sung-Sao KIM , Ju-Youn KIM , Koung-Min RYU , Jae-Hoon LEE , Tae-Won HA
IPC: H01L21/8238 , H01L29/78 , H01L27/092
CPC classification number: H01L21/823864 , H01L21/28114 , H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/092 , H01L27/0924 , H01L29/0653 , H01L29/42376 , H01L29/7854
Abstract: A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.
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