公开(公告)号：US12248700B2

公开(公告)日：2025-03-11

申请号：US17852022

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Jeongho Lee ,  Younggeon Yoo ,  Wonseb Jeong

IPC: G06F3/06

Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

公开(公告)号：US11847024B2

公开(公告)日：2023-12-19

申请号：US17972804

申请日：2022-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US11374609B2

公开(公告)日：2022-06-28

申请号：US17072512

申请日：2020-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongho Lee ,  Byungjoon Park ,  Daehyun Kang ,  Donghyun Lee ,  Jooseok Lee

IPC: H04B1/38 ,  H04B1/40 ,  H04B7/06 ,  H04B1/00

Abstract: A transceiver in a wireless communication system is provided. The transceiver includes a first circuit configured to convert a digital signal having a third bandwidth, a second circuit configured to separate the analog signal into a first analog signal corresponding to the first band and a second analog signal corresponding to the second band, up-convert the first analog signal and the second analog signal to generate a first radio frequency (RF) signal in the first band and a second RF signal in the second band, and output an RF signal having the third bandwidth, and a third circuit configured to separate the RF signal into the first RF signal and the second RF signal, adjust a phase of the first RF signal for beamforming in the first band, and adjust a phase of the second RF signal for beamforming in the second band.

公开(公告)号：US11144393B2

公开(公告)日：2021-10-12

申请号：US16840581

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

公开(公告)号：US20200152569A1

公开(公告)日：2020-05-14

申请号：US16580156

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Hoyeon Jo ,  Shanghoon Seo ,  Younggwan Ko ,  Sangkyu Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31

Abstract: A fan-out semiconductor package includes a frame having a recess portion, and a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the semiconductor chip being disposed in the recess portion. One or more through-grooves are disposed around the recess portion and each penetrate through at least a portion of the frame to each extend in a respective direction along a respective side surface of the semiconductor chip. A metal layer is disposed on side walls of the one or more through-grooves, and an encapsulant covers at least a portion of each of the frame and the semiconductor chip and fills at least a portion of the recess portion. A connection structure is disposed on the frame and the active surface of the semiconductor chip, and includes a redistribution layer electrically connected to the connection pad.

公开(公告)号：US12079080B2

公开(公告)日：2024-09-03

申请号：US18335375

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Heehyun Nam ,  Jeongho Lee ,  Younho Jeon

IPC: H03M13/15 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

公开(公告)号：US11942458B2

公开(公告)日：2024-03-26

申请号：US17511178

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohwan Lee ,  Wonkyoung Choi ,  Jeongho Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L21/56 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/20 ,  H01L24/73 ,  H01L25/0652 ,  H01L24/48 ,  H01L2224/023 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/48225 ,  H01L2224/73209 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/181

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

公开(公告)号：US20240040806A1

公开(公告)日：2024-02-01

申请号：US18125928

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Jihwang Kim ,  Jeongho Lee ,  Dongwook Kim ,  Wonkyoung Choi ,  Yunseok Choi

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/36 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253

Abstract: A semiconductor package includes a lower package, an upper package on the lower package, and an inter-package connector between the lower package and the upper package. The lower package includes a first redistribution structure, a first semiconductor chip mounted on a first mounting region of the first redistribution structure, a second semiconductor chip mounted on a second mounting region of the first redistribution structure, a molding layer on the first redistribution structure and in contact with a side wall of the first semiconductor chip and a side wall of the second semiconductor chip, and a conductive post passing through the molding layer and electrically connected to the first semiconductor chip through a first redistribution pattern of the first redistribution structure. The upper package is on the molding layer, vertically overlaps with the second mounting region of the first redistribution structure, and does not cover the first semiconductor chip.

公开(公告)号：US11669393B2

公开(公告)日：2023-06-06

申请号：US17495632

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Youngkwang Yoo ,  Younggeun Lee ,  Yena Lee

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/30 ,  G06F9/54 ,  G11C13/00 ,  G06F12/02 ,  G06F9/30

CPC classification number: G06F11/1044 ,  G06F9/30029 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0246 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

公开(公告)号：US11537471B2

公开(公告)日：2022-12-27

申请号：US17469377

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Youngsik Kim ,  Seungyou Baek ,  Eunchu Oh ,  Youngkwang Yoo ,  Younggeun Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.