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1.发明申请公开(公告)号：US20190051353A1
公开(公告)日：2019-02-14
申请号：US16161285
申请日：2018-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-chu OH , Pil-sang Yoon , Jun-jin Kong , Hong-rak Son
CPC classification number: G11C13/0069 , G06F11/1048 , G06F12/00 , G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G11C8/06 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C2013/0088 , G11C2213/71 , G11C2213/72 , H03M13/05 , H03M13/27
Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.
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2.发明授权公开(公告)号：US10748642B2
公开(公告)日：2020-08-18
申请号：US16299348
申请日：2019-03-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwang-hoon Kim , Jun-jin Kong , Hong-rak Son , Pil-sang Yoon
Abstract: A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.
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公开(公告)号：US10741245B2
公开(公告)日：2020-08-11
申请号：US16161285
申请日：2018-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-chu Oh , Pil-sang Yoon , Jun-jin Kong , Hong-rak Son
Abstract: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.
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公开(公告)号：US09647695B2
公开(公告)日：2017-05-09
申请号：US14601659
申请日：2015-01-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-jin Kim , Ung-hwan Kim , Eun-cheol Kim , Jun-jin Kong , Se-jin Lim
CPC classification number: H03M13/3738 , G06F11/1048 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/3746
Abstract: A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.
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Patent Agency Ranking
5.发明授权公开(公告)号：US09136872B2
公开(公告)日：2015-09-15
申请号：US13648421
申请日：2012-10-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-chu Oh , Jae-hong Kim , Jun-jin Kong
CPC classification number: H03M13/05 , H03M13/1102 , H03M13/356 , H03M13/3707
Abstract: A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.
Abstract translation: 存储器系统包括错误检查和校正（ECC）引擎，其被配置为根据第一方法执行临时存储在第一存储器阵列中的数据的错误校验和校正以及从第一存储器阵列读出的数据，并执行错误校验和校正 根据第二方法从第一存储器阵列读出并从第二存储器阵列读出的数据中存储在第二存储器阵列中的数据，其中响应于至少具有至少一个控制信号的控制信号选择第一方法和第二方法 第一种逻辑级别，第二种方法检查和纠正以比较第一种方法更高速率发生的数据错误。
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公开(公告)号：US09819361B2
公开(公告)日：2017-11-14
申请号：US14645073
申请日：2015-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dong-Min Shin , Jun-jin Kong , Ki-Jun Lee , Myung-Kyu Lee , Kyeong-Cheol Yang , Seung-Chan Lim
CPC classification number: H03M13/13 , H03M13/134
Abstract: A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.
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公开(公告)号：US09425828B2
公开(公告)日：2016-08-23
申请号：US14611687
申请日：2015-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
CPC classification number: H03M13/2906 , G06F11/1012 , G06F11/1044 , H03M7/30 , H03M13/05 , H03M13/6312
Abstract: A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
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8.发明授权Method of operating cyclic redundancy check in memory system and memory controller using the same 有权在存储器系统和使用其的存储器控制器中操作循环冗余校验的方法公开(公告)号：US09407289B2
公开(公告)日：2016-08-02
申请号：US14045001
申请日：2013-10-03
Applicant: Samsung Electronics Co., Ltd
Inventor： Nam-shik Kim , Dae-wook Kim , Bi-woong Chung , Jun-jin Kong
CPC classification number: H03M13/095 , G06F11/1004 , H03M13/09 , H03M13/091
Abstract: A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.
Abstract translation: 在存储器系统中执行循环冗余校验（CRC）操作的方法和使用该循环冗余校验（CRC）的存储器控制器。 该方法包括以CRC多项式初始化线性反馈移位寄存器（LFSR）电路，通过使用LFSR电路产生关于要存储在存储器件中的输入数据的CRC奇偶校验信息，以及生成关于 基于CRC奇偶校验信息的输入数据，使得LFSR电路的初始化被设置为使得LFSR电路的寄存器初始值被确定为满足以下条件：当输入到LFSR电路的数据是第一状态信息时， 从LFSR电路产生的CRC奇偶校验信息是第二状态信息。
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公开(公告)号：US20150149852A1
公开(公告)日：2015-05-28
申请号：US14611687
申请日：2015-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
CPC classification number: H03M13/2906 , G06F11/1012 , G06F11/1044 , H03M7/30 , H03M13/05 , H03M13/6312
Abstract: A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
Abstract translation: 存储器装置和存储器系统，所述存储器系统包括用于通过压缩第一单元中的程序数据产生压缩数据的数据压缩器，以及用于在第二单元中分割压缩数据的纠错块发生器，以获得多个 正常数据和生成用于校正多条正常数据的错误的纠错块，其中每个纠错块包括正常数据，具有与正常数据的大小相对应的大小的无效数据，以及用于 正常数据和无效数据。
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