公开(公告)号：US20150261905A1

公开(公告)日：2015-09-17

申请号：US14576695

申请日：2014-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HunKook LEE ,  Hongsoo Kim ,  Juyeon Lee

IPC: G06F17/50 ,  H01L21/8234 ,  H01L29/06 ,  G03F1/00 ,  H01L27/088

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F17/5081 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0653

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract translation: 提供了使用布局制造的半导体器件和半导体器件布局的方法。 准备半导体器件的布局可以包括将辅助图案布置在提供在弱有源图案上的主栅格图案附近。 弱活性图案可以是例如活性图案中最外面的一种，并且可以是预期在制造过程中具有增加的宽度的活性图案。

公开(公告)号：US20210216626A1

公开(公告)日：2021-07-15

申请号：US17003313

申请日：2020-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bohdan Karpinskyy ,  Mijung Noh ,  Jieun Park ,  Yongki Lee ,  Juyeon Lee

IPC: G06F21/55 ,  G06F7/58 ,  H03K3/84

Abstract: An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

公开(公告)号：US11651071B2

公开(公告)日：2023-05-16

申请号：US17003313

申请日：2020-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bohdan Karpinskyy ,  Mijung Noh ,  Jieun Park ,  Yongki Lee ,  Juyeon Lee

IPC: G06F21/55 ,  G06F7/58 ,  H03K3/84 ,  H03K19/20 ,  H03K19/21

CPC classification number: G06F21/552 ,  G06F7/582 ,  G06F7/588 ,  H03K3/84 ,  G06F2221/034 ,  H03K19/20 ,  H03K19/21

Abstract: An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

公开(公告)号：US09390214B2

公开(公告)日：2016-07-12

申请号：US14576695

申请日：2014-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HunKook Lee ,  Hongsoo Kim ,  Juyeon Lee

IPC: H01L21/70 ,  G06F17/50 ,  G03F1/00 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F17/5081 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0653

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract translation: 提供了使用布局制造的半导体器件和半导体器件布局的方法。 准备半导体器件的布局可以包括将辅助图案布置在提供在弱有源图案上的主栅格图案附近。 弱活性图案可以是例如活性图案中最外面的一种，并且可以是预期在制造过程中具有增加的宽度的活性图案。

公开(公告)号：US11368319B2

公开(公告)日：2022-06-21

申请号：US17015554

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsoo Kim ,  Juyeon Lee ,  Mijung Noh ,  Yongki Lee ,  Yunhyeok Choi

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/44 ,  G06F21/73

Abstract: The present disclosure relates to an integrated circuit and a method of using the integrated circuit used to perform authentication using a challenge-response method. The challenge-response method includes an internal challenge generator, a physically unclonable function (PUF) block, and a response generator. The internal challenge generator is configured to receive a challenge, generate a plurality of internal challenges corresponding to the challenge, and generate at least one valid internal challenge among the plurality of internal challenges using screen information. The physically unclonable function (PUF) block is configured to generate a plurality of valid internal responses respectively changing according to the plurality of valid internal challenges. The response generator is configured to output a response generated using the plurality of valid internal responses.

公开(公告)号：US20210234709A1

公开(公告)日：2021-07-29

申请号：US17015554

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGSOO KIM ,  Juyeon Lee ,  Mijung Noh ,  Yongki Lee ,  Yunhyeok Choi

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/73 ,  G06F21/44

Abstract: The present disclosure relates to an integrated circuit and a method of using the integrated circuit used to perform authentication using a challenge-response method. The challenge-response method includes an internal challenge generator, a physically unclonable function (PUF) block, and a response generator. The internal challenge generator is configured to receive a challenge, generate a plurality of internal challenges corresponding to the challenge, and generate at least one valid internal challenge among the plurality of internal challenges using screen information. The physically unclonable function (PUF) block is configured to generate a plurality of valid internal responses respectively changing according to the plurality of valid internal challenges. The response generator is configured to output a response generated using the plurality of valid internal responses.