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    MEMORY CONTROLLER CALCULATING OPTIMAL READ LEVEL, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY CONTROLLER
    1.
    发明申请
    MEMORY CONTROLLER CALCULATING OPTIMAL READ LEVEL, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY CONTROLLER 有权

    公开(公告)号：US20230057932A1

    公开(公告)日：2023-02-23

    申请号：US17685024

    申请日：2022-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwanwoo NOH ,  Hyeonjong SONG ,  Wijik LEE ,  Hongrak SON ,  Dongmin SHIN ,  Seonghyeog CHOI

    IPC: G06F3/06

    Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

    STORAGE DEVICE FOR HIGH SPEED LINK STARTUP AND STORAGE SYSTEM INCLUDING THE SAME
    2.
    发明申请
    STORAGE DEVICE FOR HIGH SPEED LINK STARTUP AND STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210397368A1

    公开(公告)日：2021-12-23

    申请号：US17328225

    申请日：2021-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongwoo NAM ,  Sungho SEO ,  Kwanwoo NOH ,  Myungsub SHIN ,  Haesung JUNG

    IPC: G06F3/06

    Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

    HOST CONTROLLER INTERFACE USING MULTIPLE CIRCULAR QUEUE, AND OPERATING METHOD THEREOF
    5.
    发明申请
    HOST CONTROLLER INTERFACE USING MULTIPLE CIRCULAR QUEUE, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210374079A1

    公开(公告)日：2021-12-02

    申请号：US17321916

    申请日：2021-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungsub SHIN ,  Sungho SEO ,  Kwanwoo NOH ,  Seongyong JANG ,  Haesung JUNG

    IPC: G06F13/16 ,  G06F13/18

    Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

    STORAGE DEVICE CONFIGURED TO CHANGE POWER STATE BASED ON REFERENCE CLOCK FROM HOST DEVICE AND METHOD FOR OPERATING THE SAME
    6.
    发明申请
    STORAGE DEVICE CONFIGURED TO CHANGE POWER STATE BASED ON REFERENCE CLOCK FROM HOST DEVICE AND METHOD FOR OPERATING THE SAME 有权

    公开(公告)号：US20210216223A1

    公开(公告)日：2021-07-15

    申请号：US17142627

    申请日：2021-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

    IPC: G06F3/06 ,  G06F1/04 ,  G06F9/4401

    Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.

    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME
    8.
    发明申请
    METHODS OF CONTROLLING OPERATION OF NONVOLATILE MEMORY DEVICES AND DATA CONVERTERS FOR PERFORMING THE SAME 有权

    公开(公告)号：US20210157672A1

    公开(公告)日：2021-05-27

    申请号：US16891517

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu SEOL ,  Hyejeong SO ,  Kwanwoo NOH ,  Hongrak SON ,  Pilsang YOON

    IPC: G06F11/10 ,  H03M13/13

    Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.

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