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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150200259A1

    公开(公告)日：2015-07-16

    申请号：US14474336

    申请日：2014-09-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Heun Lim ,  Myung-Jung Pyo ,  Kyung-Hyun Kim ,  Dong-Sik Kim ,  Hyo-Jung Kim

    IPC: H01L29/36 ,  H01L27/115 ,  H01L21/225 ,  H01L29/792

    CPC classification number: H01L29/36 ,  H01L21/2253 ,  H01L21/26513 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

    Abstract: A method of manufacturing a vertical-cell-type semiconductor device may include stacking alternately first insulating layers and second insulating layers on a substrate, forming a channel hole through the first and second insulating layers, and forming dielectric layers. A channel layer and a gap fill pattern may be formed within the channel hole. The channel layer may cover a top surface of an uppermost first insulating layer. The top surface of the gap fill pattern is at the same level with the top surface of the channel layer. A first conductivity type impurities may be implanted into the channel layer to form a channel impurity region. A top surface of the gap fill pattern may be recessed. A contact pad on the recessed surface of the gap fill pattern may be formed. A ground selection gate electrode, cell gate electrodes, and string selection gate electrodes may be formed in interlayer spaces that be formed by removing the second insulating layers. String selection gate electrodes may formed in the channel impurity region.

    Abstract translation: 制造垂直单元型半导体器件的方法可以包括在衬底上交替地堆叠第一绝缘层和第二绝缘层，形成通过第一和第二绝缘层的沟道孔，并形成电介质层。 可以在通道孔内形成通道层和间隙填充图案。 沟道层可以覆盖最上面的第一绝缘层的顶表面。 间隙填充图案的顶表面与通道层的顶表面处于同一水平。 可以将第一导电类型的杂质注入到沟道层中以形成沟道杂质区。 间隙填充图案的顶表面可以凹入。 可以形成间隙填充图案的凹陷表面上的接触垫。 可以在通过去除第二绝缘层形成的层间空间中形成接地选择栅电极，单元栅电极和串选择栅电极。 串选择栅电极可以形成在沟道杂质区中。

    Non-volatile memory device and method of manufacturing the same
    5.
    发明授权
    Non-volatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US09502427B2

    公开(公告)日：2016-11-22

    申请号：US15047840

    申请日：2016-02-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-Jin Shin ,  Kyung-Hyun Kim ,  Jung-Hun No ,  Choong-Kee Seong ,  Seung-Pil Chung ,  Jung-Geun Jee

    IPC: H01L21/8234 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/66825

    Abstract: A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is defined between structures including the active pattern, the preliminary tunnel insulation pattern and the preliminary charge storage pattern. A preliminary isolation pattern partially fills the trench. A dielectric layer and a control gate electrode layer are formed on the preliminary charge storage pattern and the preliminary isolation pattern. The control gate electrode layer, the dielectric layer, the preliminary charge storage pattern and the preliminary tunnel insulation pattern are patterned to form gate structures including a tunnel insulation pattern, a charge storage pattern, a dielectric layer pattern and a control gate electrode. The preliminary isolation pattern is isotropically etched to form an isolation pattern and a first air gap. An insulating interlayer is formed between the gate structures to keep the first air gap.

    Abstract translation: 在沿着一个方向延伸的每个有源图案上形成初始隧道绝缘图案和初步电荷存储图案，并且在包括有源图案，预备隧道绝缘图案和预备电荷存储图案的结构之间限定沟槽。 初步隔离图案部分地填充沟槽。 在初步电荷存储图案和初步隔离图案上形成电介质层和控制栅极电极层。 对控制栅极电极层，电介质层，预备电荷存储图案和预备隧道绝缘图案进行图案化以形成包括隧道绝缘图案，电荷存储图案，电介质层图案和控制栅电极的栅极结构。 预先隔离图案被各向同性地蚀刻以形成隔离图案和第一气隙。 在栅极结构之间形成绝缘中间层以保持第一气隙。

    Nonvolatile memory device and a method for fabricating the same
    6.
    发明授权
    Nonvolatile memory device and a method for fabricating the same 有权
    非易失存储器件及其制造方法

    公开(公告)号：US09502332B2

    公开(公告)日：2016-11-22

    申请号：US13927914

    申请日：2013-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Heun Lim ,  Hyo-Jung Kim ,  Ji-Woon Im ,  Kyung-Hyun Kim

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

    CPC classification number: H01L23/48 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

    Abstract translation: 一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部， 并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。

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