公开(公告)号：US11923283B2

公开(公告)日：2024-03-05

申请号：US17382872

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Keun Kwak

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/105 ,  H01L2225/1058

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer.

公开(公告)号：US20180175016A1

公开(公告)日：2018-06-21

申请号：US15830988

申请日：2017-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Hyun Jae Kang ,  Tae Hoi Park ,  Jin Seong Lee ,  Eun Sol Choi ,  Min Keun Kwak ,  Byung Kap Kim ,  Sung Won Choi

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

公开(公告)号：US11450614B2

公开(公告)日：2022-09-20

申请号：US17035000

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo Kim ,  Sun Chul Kim ,  Min Keun Kwak ,  Hyun Ki Kim ,  Hyung Gil Baek ,  Yong Kwan Lee

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US10573633B2

公开(公告)日：2020-02-25

申请号：US15830988

申请日：2017-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Sun Kim ,  Hyun Jae Kang ,  Tae Hoi Park ,  Jin Seong Lee ,  Eun Sol Choi ,  Min Keun Kwak ,  Byung Kap Kim ,  Sung Won Choi

IPC: H01L23/48 ,  H01L27/02 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  G03F7/20 ,  H01L23/544

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

公开(公告)号：US11862570B2

公开(公告)日：2024-01-02

申请号：US17891190

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo Kim ,  Sun Chul Kim ,  Min Keun Kwak ,  Hyun Ki Kim ,  Hyung Gil Baek ,  Yong Kwan Lee

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5385 ,  H01L21/4846 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/18 ,  H01L23/49827 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US11469133B2

公开(公告)日：2022-10-11

申请号：US16805951

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Geun Ahn ,  Min Keun Kwak ,  Ji Won Shin ,  Sang Hoon Lee ,  Byoung Wook Jang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L21/683 ,  H01L21/67 ,  B23K37/047 ,  H01L23/00 ,  B23K101/40

Abstract: A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.