公开(公告)号：US11450614B2

公开(公告)日：2022-09-20

申请号：US17035000

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo Kim ,  Sun Chul Kim ,  Min Keun Kwak ,  Hyun Ki Kim ,  Hyung Gil Baek ,  Yong Kwan Lee

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US10756075B2

公开(公告)日：2020-08-25

申请号：US16167173

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Gi Hong ,  Yong Kwan Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/18 ,  H01L23/31

Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.

公开(公告)号：US11955359B2

公开(公告)日：2024-04-09

申请号：US17200981

申请日：2021-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young Oh ,  Seung Hwan Kim ,  Jong Ho Park ,  Yong Kwan Lee ,  Jong Ho Lee

IPC: H01L21/673 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01L21/67383 ,  H01L21/6732 ,  H01L21/67346 ,  H01L21/67379 ,  H01L21/02 ,  H01L21/67017

Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.

公开(公告)号：US11862570B2

公开(公告)日：2024-01-02

申请号：US17891190

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Joo Kim ,  Sun Chul Kim ,  Min Keun Kwak ,  Hyun Ki Kim ,  Hyung Gil Baek ,  Yong Kwan Lee

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5385 ,  H01L21/4846 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/18 ,  H01L23/49827 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.

公开(公告)号：US11562965B2

公开(公告)日：2023-01-24

申请号：US17134602

申请日：2020-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Chul Kim ,  Sang Soo Kim ,  Yong Kwan Lee ,  Hyun Ki Kim ,  Seok Geun Ahn ,  Jun Young Oh

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

公开(公告)号：US12051680B2

公开(公告)日：2024-07-30

申请号：US17735158

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hwan Kim ,  Hyung Gil Baek ,  Young-Ja Kim ,  Kang Gyune Lee ,  Sang-Won Lee ,  Yong Kwan Lee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/165 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/182

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

公开(公告)号：US20240145268A1

公开(公告)日：2024-05-02

申请号：US18468192

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Woo Park ,  Gyu Hyeong Kim ,  Seung Hwan Kim ,  Jung Joo Kim ,  Jong Wan Kim ,  Yong Kwan Lee

IPC: H01L21/67 ,  H01L21/56 ,  H01L21/68

CPC classification number: H01L21/67126 ,  H01L21/565 ,  H01L21/67017 ,  H01L21/68

Abstract: A molding apparatus for fabricating a semiconductor package includes an upper mold including an upper cavity, a first side cavity at a first side of the upper cavity, a second side cavity formed at an opposite second side of the upper cavity, and a first driving part connected to the first side cavity and configured to move the first side cavity in a first direction, and a bottom mold including a bottom cavity configured to receive a molding target including a package substrate and at least one semiconductor chip. A width in the first direction between the first side cavity and the second side cavity may be smaller than a width of the package substrate in the first direction and greater than a width in the first direction between a first boundary and a second boundary of the at least one semiconductor chip.

公开(公告)号：US20210366834A1

公开(公告)日：2021-11-25

申请号：US17134602

申请日：2020-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Chul Kim ,  Sang Soo Kim ,  Yong Kwan Lee ,  Hyun Ki Kim ,  Seok Geun Ahn ,  Jun Young Oh

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

公开(公告)号：US09357652B2

公开(公告)日：2016-05-31

申请号：US14568603

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Jeong Kim ,  Yong Kwan Lee

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H05K3/06 ,  H01L23/13 ,  H01L23/498 ,  H01L23/14

CPC classification number: H05K3/06 ,  H01L21/486 ,  H01L21/52 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29036 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/041 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A method of manufacturing a circuit board may include: preparing a circuit board body including an insulating layer having a first surface and a second surface opposite to the first surface and a first conductive thin film layer disposed on the first surface of the insulating layer and having a convex portion which is disposed on a first surface of the first conductive thin film layer and is embedded in the insulating layer; removing the convex portion to form a cavity corresponding to the convex portion in the insulating layer; and forming one or more first wiring patterns on the first surface of the insulating layer by removing first portions of the first conductive thin film layer. The one or more first wiring patterns correspond to second portions of the first conductive thin film layer not removed.

Abstract translation: 制造电路板的方法可以包括：制备电路板主体，其包括具有第一表面和与第一表面相对的第二表面的绝缘层，以及设置在绝缘层的第一表面上的第一导电薄膜层，并且具有 凸部，其设置在所述第一导电性薄膜层的第一表面上并嵌入所述绝缘层中; 去除所述凸部以形成与所述绝缘层中的所述凸部对应的空腔; 以及通过去除第一导电薄膜层的第一部分，在绝缘层的第一表面上形成一个或多个第一布线图案。 一个或多个第一布线图案对应于未被去除的第一导电薄膜层的第二部分。