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    Semiconductor devices and electronic systems including the same
    1.
    发明授权
    Semiconductor devices and electronic systems including the same 有权

    公开(公告)号：US12262534B2

    公开(公告)日：2025-03-25

    申请号：US17667156

    申请日：2022-02-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wooyong Jeon ,  Moorym Choi

    IPC: H10B41/40 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

    SEMICONDUCTOR DEVICES
    3.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230140000A1

    公开(公告)日：2023-05-04

    申请号：US17834977

    申请日：2022-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym Choi ,  Jungtae Sung ,  Yunsun Jang

    IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/417

    Abstract: A semiconductor device includes first and second substrates including cell and peripheral circuit regions, first and second gate electrode structures, first and second channels, and first to third transistors. The first and second gate electrode structures include first and second gate electrodes in a vertical direction. The first and second channel extend through the first and second gate electrode structures. The first transistor is on the peripheral circuit region. The second gate electrode structure is on the first gate electrode structure and the first transistor. The second and third transistors are on the second gate electrode structure. The second substrate is on the second and third transistors. The first and second channels do not directly contact each other, are electrically connected with each other, and receive electrical signals from the second transistor. The first and third transistors apply electrical signals to the first and second gate electrode structures.

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US12302578B2

    公开(公告)日：2025-05-13

    申请号：US17834977

    申请日：2022-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym Choi ,  Jungtae Sung ,  Yunsun Jang

    IPC: H10B43/40 ,  H01L23/528 ,  H10B43/27 ,  H10D64/23

    Abstract: A semiconductor device includes first and second substrates including cell and peripheral circuit regions, first and second gate electrode structures, first and second channels, and first to third transistors. The first and second gate electrode structures include first and second gate electrodes in a vertical direction. The first and second channel extend through the first and second gate electrode structures. The first transistor is on the peripheral circuit region. The second gate electrode structure is on the first gate electrode structure and the first transistor. The second and third transistors are on the second gate electrode structure. The second substrate is on the second and third transistors. The first and second channels do not directly contact each other, are electrically connected with each other, and receive electrical signals from the second transistor. The first and third transistors apply electrical signals to the first and second gate electrode structures.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20230138478A1

    公开(公告)日：2023-05-04

    申请号：US17977689

    申请日：2022-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym Choi ,  Junyoung Choi

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: A semiconductor device includes: a first substrate; circuit devices disposed on the first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure bonded to the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate disposed on the upper interconnection structure; a conductive plate disposed below the second substrate; gate electrodes disposed between the upper interconnection structure and the conductive plate and stacked in a vertical direction; channel structures penetrating through the gate electrodes; a plurality of conductive patterns, respectively disposed in a plurality of openings penetrating through the second substrate; and a peripheral contact plug extending in the vertical direction in an external region from the conductive plate and being connected to one of the plurality of conductive patterns.

    Non-volatile memory device with a conductive etch stop layer, method of manufacturing the same, and memory system including the same
    8.
    发明授权
    Non-volatile memory device with a conductive etch stop layer, method of manufacturing the same, and memory system including the same 有权

    公开(公告)号：US12278201B2

    公开(公告)日：2025-04-15

    申请号：US17825076

    申请日：2022-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym Choi ,  Yunsun Jang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

    Abstract: Provided is a non-volatile memory device including a first structure including a first substrate; a peripheral circuit; a first insulation structure; a plurality of first bonding pads; and a first interconnect structure; a second structure, which includes a conductive etch stop layer; a common source line layer; a stacked structure including alternately stacked gate layers and interlayer insulation layers; a plurality of channel structures penetrating through a cell region of the stacked structure; a second insulation structure; a plurality of second bonding pads; and a second interconnect structure and bonded to the first structure; and a connection layer including a third insulation structure; an input/output via; and an input/output pad, wherein an interface between the second insulation structure and the third insulation structure is disposed at a vertical level between the top surface and the bottom surface of the conductive etch stop layer.

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