公开(公告)号：US20220246610A1

公开(公告)日：2022-08-04

申请号：US17221355

申请日：2021-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghyun SONG ,  Seungyoung LEE ,  Saehan PARK

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

公开(公告)号：US20250031360A1

公开(公告)日：2025-01-23

申请号：US18905663

申请日：2024-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Saehan PARK ,  Seungyoung LEE ,  Inchan HWANG

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US20220336355A1

公开(公告)日：2022-10-20

申请号：US17361996

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Hoonseok SEO ,  Kang Ill SEO

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522

Abstract: Provided is a semiconductor architecture including a wafer, a semiconductor device provided on the wafer, the semiconductor device including an epitaxial layer, an epitaxial contact provided on the epitaxial layer, a first via provided on the epitaxial contact, and metal lines provided on the first via, the metal lines being configured to route signals, an oxide layer provided on a first surface of the wafer and adjacent to the semiconductor device, and a buried power rail (BPR) configured to deliver power, at least a portion of the BPR being included inside of the wafer, wherein a portion of the BPR contacts the oxide layer.

公开(公告)号：US20220230947A1

公开(公告)日：2022-07-21

申请号：US17220664

申请日：2021-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Seungyoung Lee

IPC: H01L23/498 ,  H01L23/528 ,  H01L21/48

Abstract: Provided is a backside power distribution network (BSPDN) semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device including an active device that includes an epitaxial layer, a second semiconductor device provided on a second surface of the wafer opposite to the first surface, the second semiconductor device including a power rail configured to supply power, and a through-silicon via (TSV) protruding from the power rail and extending to a level of the epitaxial layer of the active device.

公开(公告)号：US20230343825A1

公开(公告)日：2023-10-26

申请号：US17988485

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Panjae PARK ,  Seungyoung LEE ,  Byounghak HONG ,  Gunho JO

IPC: H01L29/06 ,  H01L27/06 ,  H01L23/48 ,  H01L29/08 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/78696 ,  H01L27/0886

Abstract: Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region

公开(公告)号：US20240063123A1

公开(公告)日：2024-02-22

申请号：US18386497

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/5286 ,  H01L27/0694 ,  H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/53257

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

公开(公告)号：US20230411294A1

公开(公告)日：2023-12-21

申请号：US18457000

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20220230961A1

公开(公告)日：2022-07-21

申请号：US17220643

申请日：2021-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Seungyoung LEE

IPC: H01L23/528

Abstract: Provided is a semiconductor architecture having a metal-oxide-semiconductor field-effect transistor (MOSFET) cell, the semiconductor architecture including a first semiconductor device included in the MOSFET cell, a second semiconductor device included in the MOSFET cell, the second semiconductor device being provided above the first semiconductor device, a first power rail configured to supply power to the first semiconductor device, the first power rail being provided at a vertical level different from the first semiconductor device and the second semiconductor device, and a second power rail configured to supply power to the second semiconductor device, the second power rail being provided at a vertical level between the first semiconductor device and the second semiconductor device.