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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240413151A1

    公开(公告)日：2024-12-12

    申请号：US18808934

    申请日：2024-08-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungho DO ,  Sanghoon Baek

    IPC: H01L27/088 ,  H01L23/50 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10050058B2

    公开(公告)日：2018-08-14

    申请号：US15282206

    申请日：2016-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

    IPC: H01L21/8238 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11582

    Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

    High density field effect transistor design including a broken gate line
    5.
    发明授权
    High density field effect transistor design including a broken gate line 有权
    高密度场效应晶体管的设计包括一条断线

    公开(公告)号：US09117051B2

    公开(公告)日：2015-08-25

    申请号：US14059093

    申请日：2013-10-21

    Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

    Inventor： Chieh-yu Lin ,  Kehan Tian ,  Sanghoon Baek

    IPC: G06F17/50 ,  H01L21/033 ,  H01L21/8234

    CPC classification number: G06F17/5072 ,  H01L21/32139 ,  H01L21/823475 ,  H01L27/0207

    Abstract: A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.

    Abstract translation: 设计布局包括一组表示半导体有源区域的有源区域级设计形状，以及一组表示栅极线跨越半导体有源区域的门级设计形状。 门级设计形状的集合包括连接两个门级设计形状的子分辨率辅助特征（SRAF），并且在使用光刻方法打印时物理地表现为两条栅极线之间的间隙。 可以使用包括具有突出水龙头的切割级设计形状的切割掩模来切割靠近半导体有源区域的栅极线的边缘。 突出的抽头允许可靠地去除栅极线的端部，并且防止由不想要的残留栅极结构破坏升高的源极和漏极区域。

    HIGH DENSITY FIELD EFFECT TRANSISTOR DESIGN INCLUDING A BROKEN GATE LINE
    6.
    发明申请
    HIGH DENSITY FIELD EFFECT TRANSISTOR DESIGN INCLUDING A BROKEN GATE LINE 有权
    高密度场效应晶体管设计，包括一个断开的门线

    公开(公告)号：US20150111367A1

    公开(公告)日：2015-04-23

    申请号：US14059093

    申请日：2013-10-21

    Applicant: Samsung Electronics Co., Ltd. ,  International Business Machines Corporation

    Inventor： Chieh-yu Lin ,  Kehan Tian ,  Sanghoon Baek

    IPC: G06F17/50 ,  H01L21/8234 ,  H01L21/033

    CPC classification number: G06F17/5072 ,  H01L21/32139 ,  H01L21/823475 ,  H01L27/0207

    Abstract: A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.

    Abstract translation: 设计布局包括一组表示半导体有源区域的有源区域级设计形状，以及一组表示栅极线跨越半导体有源区域的门级设计形状。 门级设计形状的集合包括连接两个门级设计形状的子分辨率辅助特征（SRAF），并且在使用光刻方法打印时物理地表现为两条栅极线之间的间隙。 可以使用包括具有突出水龙头的切割级设计形状的切割掩模来切割靠近半导体有源区域的栅极线的边缘。 突出的抽头允许可靠地去除栅极线的端部，并且防止由不想要的残留栅极结构破坏升高的源极和漏极区域。

    Semiconductor devices having improved layout designs, and methods of designing and fabricating the same
    7.
    发明授权
    Semiconductor devices having improved layout designs, and methods of designing and fabricating the same 有权

    公开(公告)号：US12218121B2

    公开(公告)日：2025-02-04

    申请号：US17373510

    申请日：2021-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Do ,  Sanghoon Baek

    IPC: G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092

    Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11842964B2

    公开(公告)日：2023-12-12

    申请号：US17323407

    申请日：2021-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS
    10.
    发明公开
    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20230297752A1

    公开(公告)日：2023-09-21

    申请号：US18162120

    申请日：2023-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Sanghoon Baek

    IPC: G06F30/392

    CPC classification number: G06F30/392

    Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.

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