公开(公告)号：US11469099B2

公开(公告)日：2022-10-11

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US20220020713A1

公开(公告)日：2022-01-20

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L23/00 ,  H01L25/065

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

公开(公告)号：US11362062B2

公开(公告)日：2022-06-14

申请号：US17142133

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Hwang ,  Unbyoung Kang ,  Sangsick Park ,  Jihwan Suh ,  Soyoun Lee ,  Teakhoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20210143008A1

公开(公告)日：2021-05-13

申请号：US16905310

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Ko ,  Hyeongmun Kang ,  Sangsick Park ,  Hyeonjun Song

IPC: H01L21/02 ,  H01L21/56 ,  H01L21/762

Abstract: A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

公开(公告)号：US20240186289A1

公开(公告)日：2024-06-06

申请号：US18226990

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin Lee ,  Unbyoung Kang ,  Seongyo Kim ,  Sangsick Park

IPC: H01L25/065 ,  H01L21/461 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/461 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/32 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/32145

Abstract: A method of manufacturing a semiconductor package comprises stacking, via an adhesive member, a plurality of memory dies to form a memory die stack on a buffer die; forming a first molding member on the buffer die to cover the memory die stack; polishing an upper surface of the first molding member to expose an upper surface of an uppermost memory die in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack; removing edge portions of the uppermost memory die together with at least a portion of the first molding member and at least a portion of the adhesive member to form a stepped portion; and forming a second molding member on the first molding member to cover the stepped portion of the uppermost memory die.

公开(公告)号：US11688707B2

公开(公告)日：2023-06-27

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05551 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2225/06513

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

公开(公告)号：US20250079378A1

公开(公告)日：2025-03-06

申请号：US18949707

申请日：2024-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.

公开(公告)号：US12176313B2

公开(公告)日：2024-12-24

申请号：US17652782

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.

公开(公告)号：US20240128221A1

公开(公告)日：2024-04-18

申请号：US18367642

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsoo Kim ,  Seongyo Kim ,  Sangsick Park ,  Soyoun Lee

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L24/27 ,  H01L2224/16148 ,  H01L2224/278 ,  H01L2224/29018 ,  H01L2224/29552 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/381

Abstract: According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes a substrate including a first surface and a second surface opposite to the first surface; and a plurality of lower pads on the second surface at different intervals. The semiconductor package further includes: a plurality of bumps attached to the plurality of lower pads; a first non-conductive film on the second surface of the substrate; and a second non-conductive film on the first non-conductive film. A plurality of regions are defined in the semiconductor package according to a separation distance between the plurality of bumps, such that each region of the plurality of regions includes respective bumps, from among the plurality of bumps, that have a respective separation distance between neighboring ones of the respective bumps within the region. A sum of thicknesses of the first and second non-conductive films is constant.

公开(公告)号：US11791308B2

公开(公告)日：2023-10-17

申请号：US17804110

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Hwang ,  Unbyoung Kang ,  Sangsick Park ,  Jihwan Suh ,  Soyoun Lee ,  Teakhoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/83 ,  H01L23/49816 ,  H01L24/13 ,  H01L25/0657

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.