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    Method for fabricating semiconductor device
    1.
    发明授权
    Method for fabricating semiconductor device 有权

    公开(公告)号：US11476194B2

    公开(公告)日：2022-10-18

    申请号：US17316798

    申请日：2021-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok Han Park

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/311

    Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11469252B2

    公开(公告)日：2022-10-11

    申请号：US16942093

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Han Park ,  Yong Seok Kim ,  Hui-Jung Kim ,  Satoru Yamada ,  Kyung Hwan Lee ,  Jae Ho Hong ,  Yoo Sang Hwang

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240119978A1

    公开(公告)日：2024-04-11

    申请号：US18329067

    申请日：2023-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Woo Han ,  Hyun Geun Choi ,  Ki Seok Lee ,  Seok Han Park

    IPC: G11C7/18 ,  G11C5/06 ,  G11C7/12

    CPC classification number: G11C7/18 ,  G11C5/063 ,  G11C7/12

    Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250081445A1

    公开(公告)日：2025-03-06

    申请号：US18660803

    申请日：2024-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bo Won Yoo ,  Seok Han Park ,  Keun Ui Kim ,  Yu Jin Kim ,  Joong Chan Shin ,  Gyu Hwan Oh ,  Eun Suk Jang ,  Jin Woo Han

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a bit line extending in a first direction on a substrate, an active pattern on the bit line, a word line on a first sidewall of the active pattern and extending in a second direction, a back gate electrode on a second sidewall of the active pattern and extending in the second direction, a gate isolation pattern on the first sidewall of the active pattern and including a low-k pattern extending in the second direction, and a data storage pattern connected to the second surface of the active pattern. The word line is between the active pattern and the gate isolation pattern, and a vertical distance between the bit line and the word line is greater than a vertical distance between the bit line and the low-k pattern.

    Semiconductor device and method for fabricating the same
    8.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US11031338B2

    公开(公告)日：2021-06-08

    申请号：US16528839

    申请日：2019-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok Han Park

    IPC: H01L23/528 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

    Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.

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