公开(公告)号：US20160132414A1

公开(公告)日：2016-05-12

申请号：US14980903

申请日：2015-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Chul CHO ,  Seong-Hoon JEONG ,  Jin-Sae JUNG

IPC: G06F11/26 ,  G06F11/263

CPC classification number: G06F11/261 ,  G06F11/263 ,  G06F17/5009

Abstract: A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

Abstract translation: 公开了一种模拟装置和配电仿真系统。 根据一个示例，模拟装置包括被配置为执行模拟任务的模拟执行器，被配置为基于在执行模拟任务之前设置的数据存储策略来存储与模拟任务相关的数据的数据存储 以及数据更新器，被配置为通过将存储在数据存储器中的数据与存储在另一模拟装置中的数据进行比较来将存储在数据存储器中的数据更新为最新数据。

公开(公告)号：US20190013401A1

公开(公告)日：2019-01-10

申请号：US16128152

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Kyung-Seok OH ,  Cheol KIM ,  Heon-Jong SHIN ,  Jong-Ryeol YOO ,  Hyun-Jung LEE ,  Seong-Hoon JEONG

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US20140374827A1

公开(公告)日：2014-12-25

申请号：US14259212

申请日：2014-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Chan SUH ,  Chung-Geun KOH ,  Seong-Hoon JEONG ,  Kwan-Heum LEE ,  Hwa-Sung RHEE ,  Gyeom KIM

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain.

Abstract translation: 半导体器件包括突出在器件隔离层上方的翅片型有源图案，器件隔离层上的栅电极并与鳍式有源图案相交，栅极电极两侧的翅片型有源图案上的升高的源极/漏极 以及在翅片型有源图案的侧壁上的翅片间隔件，翅片间隔件具有低介电常数并且位于器件隔离层和升高的源极/漏极之间。

公开(公告)号：US20130175491A1

公开(公告)日：2013-07-11

申请号：US13729742

申请日：2012-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jong HAN ,  Kong-Soo LEE ,  Yoon-Goo KANG ,  Ho-Kyun AN ,  Seong-Hoon JEONG

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Abstract translation: 半导体器件及其制造方法包括半导体衬底中的场区以限定有源区。 层间绝缘层位于半导体衬底上。 半导体图案在垂直延伸穿过层间绝缘层的孔内。 半导体图案与有源区域接触。 阻挡区域在半导体图案和层间绝缘层之间。 阻挡区域包括第一缓冲介电材料和阻挡介电材料。 第一缓冲电介质材料在阻挡介电材料和半导体图案之间，并且阻挡介电材料与半导体图案和有源区两者间隔开。