公开(公告)号：US20160323096A1

公开(公告)日：2016-11-03

申请号：US14699354

申请日：2015-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Michael KARA-IVANOV ,  Vadim BUGAENKO ,  Yaron SHANY ,  Jun Jin KONG ,  Shay LANDIS ,  Shmuel DASHEVSKY

IPC: H04L9/00 ,  G06F21/44 ,  G06F21/75 ,  H04L9/08

CPC classification number: H04L9/002 ,  G06F21/44 ,  G06F21/73 ,  H04L9/0861 ,  H04L9/0866

Abstract: A method generating a cryptographic key and corresponding helper data includes measuring an analog value associated with a physical property of cells of a memory array; digitizing the measured analog value to generate the cryptographic key; quantizing the measured analog value to generate the corresponding non-leaky helper data.

Abstract translation: 产生加密密钥和对应的辅助数据的方法包括测量与存储器阵列的单元的物理属性相关联的模拟值; 数字化测量的模拟值以产生加密密钥; 量化测量的模拟值以生成相应的非泄漏辅助数据。

公开(公告)号：US20130205075A1

公开(公告)日：2013-08-08

申请号：US13756784

申请日：2013-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moshe TWITTO ,  Rutie ADAR ,  Shay LANDIS

IPC: G11C16/26 ,  G06F12/02 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F12/0246 ,  G11C5/141 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/3431 ,  G11C16/3459

Abstract: There is provided a nonvolatile memory device including a memory cell array including nonvolatile memory cells, a battery not supplied with external power and configured to store a charged voltage, a sensing unit configured to sense a degradation state of the nonvolatile memory cells of the memory cell array, and a trigger circuit configured to transmit a refresh trigger signal based on the sensing result, wherein the nonvolatile memory cells of the memory cell array are refreshed using the charged voltage provided by the battery in response to the trigger signal transmitted from the trigger circuit.

Abstract translation: 提供一种包括非易失性存储单元的存储单元阵列，未被提供外部电源并被配置为存储充电电压的电池的非易失性存储器件，被配置为感测存储单元的非易失性存储单元的劣化状态的感测单元 阵列和触发电路，其被配置为基于所述感测结果发送刷新触发信号，其中所述存储单元阵列的非易失性存储单元响应于从所述触发电路发送的触发信号，使用由所述电池提供的充电电压来刷新 。

公开(公告)号：US20160117256A1

公开(公告)日：2016-04-28

申请号：US14523159

申请日：2014-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Avner DOR ,  Elona EREZ ,  Shay LANDIS ,  Jun Jin KONG

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.

Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。

公开(公告)号：US20170139769A1

公开(公告)日：2017-05-18

申请号：US14941051

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Evgeny BLAICHMAN ,  Moshe TWITTO ,  Avner DOR ,  Elona EREZ ,  Jun Jin KONG ,  Shay LANDIS ,  Yaron SHANY ,  Yoav SHERESHEVSKI

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/455

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.