公开(公告)号：US20220206966A1

公开(公告)日：2022-06-30

申请号：US17467929

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongsu KIM ,  Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

IPC: G06F13/16 ,  H04L7/00 ,  H04L1/00 ,  G06F13/40 ,  G06F1/12

Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.

公开(公告)号：US20250021129A1

公开(公告)日：2025-01-16

申请号：US18897011

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20210216223A1

公开(公告)日：2021-07-15

申请号：US17142627

申请日：2021-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

IPC: G06F3/06 ,  G06F1/04 ,  G06F9/4401

Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.

公开(公告)号：US20200051601A1

公开(公告)日：2020-02-13

申请号：US16655782

申请日：2019-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwoo JEONG ,  Hwaseok OH ,  JinHyeok CHOI

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/08 ,  G11C16/32 ,  G11C29/02

Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

公开(公告)号：US20180090191A1

公开(公告)日：2018-03-29

申请号：US15685654

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongwoo JEONG ,  Hwaseok OH ,  JinHyeok CHOI

IPC: G11C7/22 ,  G11C16/08 ,  G11C16/32 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/12 ,  G11C16/08 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.

公开(公告)号：US20210263550A1

公开(公告)日：2021-08-26

申请号：US17179830

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20240085940A1

公开(公告)日：2024-03-14

申请号：US18508479

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/4291 ,  G11C7/22 ,  G11C16/32 ,  H04L7/0004 ,  H04L7/0008

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20230385209A1

公开(公告)日：2023-11-30

申请号：US18446670

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongsu KIM ,  Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG

IPC: G06F13/16 ,  H04L7/00 ,  G06F1/12 ,  G06F13/40 ,  H04L1/00

CPC classification number: G06F13/1668 ,  H04L7/0008 ,  G06F1/12 ,  G06F13/4027 ,  H04L1/0002

Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.

公开(公告)号：US20230112284A1

公开(公告)日：2023-04-13

申请号：US18064002

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06 ,  G11C7/22 ,  G11C16/32 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.