公开(公告)号：US20230163076A1

公开(公告)日：2023-05-25

申请号：US17885025

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ki PARK ,  Yoon Tae Hwang ,  Wan Don Kim ,  Sung Hwan Kim ,  Tae Yeol Kim

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76895

Abstract: A semiconductor device includes a gate structure including a gate electrode on a substrate. A source/drain pattern is on the substrate and positioned on a side surface of the gate electrode. A source/drain contact is on the source/drain pattern. A first conductive pad is on the source/drain contact. A second conductive pad is on the gate structure. A via plug penetrates the first conductive pad and is connected to the source/drain contact. A gate contact penetrates the second conductive pad and is connected to the gate electrode. A portion of the via plug protrudes from the first conductive pad. A portion of the gate contact protrudes from the second conductive pad. A height from an upper surface of the gate structure to an upper surface of the via plug is equal to a height from the upper surface of the gate structure to an upper surface of the gate contact.

公开(公告)号：US20220208679A1

公开(公告)日：2022-06-30

申请号：US17475141

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wan Don Kim ,  Hyun Bae Lee ,  Yoon Tae Hwang

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/48

Abstract: A FINFET includes a substrate having a semiconductor fin extending upward from a first surface thereof, and first and second power rails on first and second opposing sides of the semiconductor fin, respectively. A base of the semiconductor fin may be recessed within a trench within the surface of the substrate, and the first and second power rails may at least partially fill the trench. A through-substrate via may be provided, which extends from adjacent a second surface of the substrate to at least one of the first and second power rails. A source/drain contact is also provided, which is electrically connected to a source/drain region of the FINFET and at least one of the first and second power rails.

公开(公告)号：US10217640B2

公开(公告)日：2019-02-26

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/51 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US12183742B2

公开(公告)日：2024-12-31

申请号：US18600403

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20230135806A1

公开(公告)日：2023-05-04

申请号：US17821033

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghwan Kim ,  Geunwoo Kim ,  Wandon Kim ,  Yoon Tae Hwang

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern that are on the active pattern and connected to each other, and an active contact electrically connected to the source/drain pattern. The active contact includes a first barrier metal and a first filler metal on the first barrier metal, and the first barrier metal includes a metal nitride layer. The first filler metal includes at least one of molybdenum, tungsten, ruthenium, cobalt, or vanadium. The first filler metal includes a first crystalline region having a body-centered cubic (BCC) structure and a second crystalline region having a face-centered cubic (FCC) structure. A proportion of the first crystalline region in the first filler metal ranges from 60% to 99%.

公开(公告)号：US11417656B2

公开(公告)日：2022-08-16

申请号：US16898719

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US11830874B2

公开(公告)日：2023-11-28

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/4941

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US11682706B2

公开(公告)日：2023-06-20

申请号：US17588670

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41766 ,  H01L21/28518 ,  H01L21/76843 ,  H01L23/53209 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US11233050B2

公开(公告)日：2022-01-25

申请号：US16860279

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US10181427B2

公开(公告)日：2019-01-15

申请号：US15858403

申请日：2017-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyun Song ,  Yoon Tae Hwang ,  Kyu Min Lee ,  Soo Jung Choi

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.