公开(公告)号：US20210320039A1

公开(公告)日：2021-10-14

申请号：US17356152

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Jae LEE ,  Sang-Lok KIM ,  Byung-Hoon JEONG ,  Tae-Sung LEE ,  Jeong-Don IHM ,  Jae-Yong JEONG ,  Young-Don CHOI

IPC: H01L21/66 ,  H01L23/528 ,  G01R31/3187

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US20190198067A1

公开(公告)日：2019-06-27

申请号：US16113500

申请日：2018-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Dae-Hoon NA ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  H01L25/065

CPC classification number: G11C7/1051 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/14 ,  G11C7/222 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

公开(公告)号：US20170288717A1

公开(公告)日：2017-10-05

申请号：US15397012

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo LEE ,  Byung-Hoon JEONG ,  Jeong-Don IHM ,  Young-Don CHOI

IPC: H04B1/24 ,  H04L25/03 ,  H04L12/863

CPC classification number: H04B1/24 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03847 ,  H04L25/03878 ,  H04L47/6235 ,  H04L49/90

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

公开(公告)号：US20130308377A1

公开(公告)日：2013-11-21

申请号：US13781997

申请日：2013-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Don CHOI ,  Mu-Hui PARK ,  Hyun-Kook PARK ,  Ickhyun SONG

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/0069 ,  G11C2213/72

Abstract: A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

Abstract translation: 感测电路包括多个单元读取电流发生器，参考电流发生器和多个读出放大器。 每个单元读取电流发生器从多个存储器单元中的每一个生成单元读取电流。 参考电流发生器将单元读取电流相加以产生和电流。 每个读出放大器基于每个单元读取电流和平均电流来确定存储在每个存储器单元中的数据状态。 平均电流是根据和电流获得的。