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    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME
    2.
    发明申请
    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220157353A1

    公开(公告)日：2022-05-19

    申请号：US17361780

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joohwan KIM ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G11C7/10 ,  G06F3/06 ,  G11C7/22

    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM
    3.
    发明申请
    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM 有权

    公开(公告)号：US20220068331A1

    公开(公告)日：2022-03-03

    申请号：US17230403

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu LEE ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Hyungmin JIN ,  Junghwan CHOI

    IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16

    Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20240370386A1

    公开(公告)日：2024-11-07

    申请号：US18772354

    申请日：2024-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
    5.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230353132A1

    公开(公告)日：2023-11-02

    申请号：US18219254

    申请日：2023-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K5/06 ,  H03K5/05 ,  H03K5/15

    CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K5/1506 ,  H03K5/1508

    Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT
    7.
    发明申请
    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT 有权

    公开(公告)号：US20220385287A1

    公开(公告)日：2022-12-01

    申请号：US17751148

    申请日：2022-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K17/693 ,  H03K19/20

    Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

    CLOCK SIGNAL DELAY PATH UNIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    10.
    发明申请
    CLOCK SIGNAL DELAY PATH UNIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230072675A1

    公开(公告)日：2023-03-09

    申请号：US17695168

    申请日：2022-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K5/06 ,  H03K5/15 ,  H03K5/05

    Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

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