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公开(公告)号:US09990912B2
公开(公告)日:2018-06-05
申请号:US15233506
申请日:2016-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung-Min Kim , Min-Hee Lee , Yun-Jae Lee
CPC classification number: G10H1/34 , G10H1/183 , G10H7/00 , G10H2220/106 , G10H2220/201 , G10H2220/241 , G10H2230/015
Abstract: An electronic device and a method for reproducing a sound in the electronic device are provided. The electronic device includes a touchscreen displaying a keyboard having a plurality of keys and a plurality of sound source buttons corresponding respectively to a plurality of different sound sources, a processor connected electrically to the touchscreen, and a memory connected electrically to the processor, wherein the memory stores instructions that are executed to cause the processor to perform control such that when an input to at least one key among the plurality of keys is received, the sound source corresponding to at least one sound source button selected among the plurality of sound source buttons is reproduced as a sound corresponding to the received input.
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公开(公告)号:USD774520S1
公开(公告)日:2016-12-20
申请号:US29529570
申请日:2015-06-09
Applicant: Samsung Electronics Co., Ltd.
Designer: Sung-Min Kim , Han-Gyul Kim , Min-Hee Lee , Yun-Jae Lee
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公开(公告)号:USD766953S1
公开(公告)日:2016-09-20
申请号:US29513854
申请日:2015-01-06
Applicant: Samsung Electronics Co., Ltd.
Designer: Han-Gyul Kim , Sung-Min Kim , Chang-Hwan Kim , Min-Hee Lee , Yun-Jae Lee
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公开(公告)号:US09666789B2
公开(公告)日:2017-05-30
申请号:US14741446
申请日:2015-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
CPC classification number: H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
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