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    System and method for measuring current
    1.
    发明申请
    System and method for measuring current 失效
    用于测量电流的系统和方法

    公开(公告)号：US20050040901A1

    公开(公告)日：2005-02-24

    申请号：US10644542

    申请日：2003-08-20

    申请人： Christopher Bostak ,  Samuel Naffziger ,  Christopher Poirier ,  Eric Fetzer

    发明人： Christopher Bostak ,  Samuel Naffziger ,  Christopher Poirier ,  Eric Fetzer

    IPC分类号： G01R31/28 ,  G01R19/00 ,  G01R19/252 ,  H03B1/00

    CPC分类号： G01R19/252 ,  G01R19/0092

    摘要： The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

    摘要翻译： 本发明涉及一种用于测量集成电路中的电流的系统和方法，包括使用第一测量电压测量来自第一压控振荡器（VCO）的第一输出计数，同时使用第二测量电压测量来自第二VCO的第二输出计数 第二测量电压，并且使用与第一和第二输出计数之间的差成比例的电压来计算集成电路中的电流。

    System toTemporarily Modify an Output Waveform
    4.
    发明申请
    System toTemporarily Modify an Output Waveform 失效
    系统暂时修改输出波形

    公开(公告)号：US20050040870A1

    公开(公告)日：2005-02-24

    申请号：US10646936

    申请日：2003-08-22

    申请人： Samuel Naffziger ,  Eric Fetzer

    发明人： Samuel Naffziger ,  Eric Fetzer

    IPC分类号： G01R31/28 ,  G01R31/319 ,  H03K5/06 ,  H03K19/0185 ,  H03K4/90

    CPC分类号： H03K5/06 ,  G01R31/2856 ,  G01R31/31928 ,  H03K19/018585

    摘要： Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

    摘要翻译： 公开了用于提供临时修改的输出的系统和方法。 波形控制提供在第一操作模式期间临时调整到正常高电平和低电平之间的中间电平的控制输出。 波形控制提供控制输出以在第二操作模式期间在高电平和低电平之间周期性地跳变。 延迟网络控制波形控制，以在第一操作模式期间的中间级提供输出持续一段时间。

    Power estimation based on power characterizations of non-conventional circuits
    5.
    发明申请
    Power estimation based on power characterizations of non-conventional circuits 审中-公开
    基于非常规电路的功率特性的功率估计

    公开(公告)号：US20050050494A1

    公开(公告)日：2005-03-03

    申请号：US10653328

    申请日：2003-09-02

    申请人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

    发明人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/78

    摘要： Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations to determine power consumption associated with non-conventional circuits in the circuit design. The power characterizations can be determined prior to circuit design timing analysis, stored and utilized during circuit design timing analysis. The power estimates associated with the non-conventional circuits can be added to power estimates associated with the conventional circuits of the circuit design to compute a power associated with the circuit design.

    摘要翻译： 提供了可用于估计与电路设计相关联的功率的系统和方法。 通过使用功率特征来确定在电路设计中与非常规电路相关联的功率消耗来确定估计功率。 功率特征可以在电路设计时序分析之前确定，在电路设计时序分析期间存储和利用。 与非常规电路相关联的功率估计可以被添加到与电路设计的常规电路相关联的功率估计，以计算与电路设计相关联的功率。

    Managing power consumption in a multi-core processor
    6.
    发明授权
    Managing power consumption in a multi-core processor 有权
    管理多核处理器的功耗

    公开(公告)号：US09069555B2

    公开(公告)日：2015-06-30

    申请号：US13422476

    申请日：2012-03-16

    申请人： Eric Fetzer ,  Reid J. Reidlinger ,  Don Soltis ,  William J. Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    发明人： Eric Fetzer ,  Reid J. Reidlinger ,  Don Soltis ,  William J. Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

    摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的动态电容来控制核心区域消耗的功率，使得动态电容在允许的动态电容值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

    METHOD AND CIRCUIT FOR MEASURING ON-CHIP, CYCLE-TO-CYCLE CLOCK JITTER
    7.
    发明申请
    METHOD AND CIRCUIT FOR MEASURING ON-CHIP, CYCLE-TO-CYCLE CLOCK JITTER 失效
    用于测量片上，周期到周期时钟抖动的方法和电路

    公开(公告)号：US20050024037A1

    公开(公告)日：2005-02-03

    申请号：US10630175

    申请日：2003-07-29

    申请人： Eric Fetzer

    发明人： Eric Fetzer

    IPC分类号： G01R25/00 ,  G01R31/317 ,  G01R23/00 ,  G01R23/12

    CPC分类号： G01R31/31709 ,  G01R25/005 ,  G01R31/31725

    摘要： The invention provides a method and circuit for measuring on-chip, cycle-to-cycle, jitter. Copies of a circuit comprising a programmable delay line, a programmable phase comparator, and two counters are placed at different locations on an IC near a clock signal. The programmable delay line creates a clock signal that is delayed by one clock cycle. This delayed clock signal is compared in time to the original clock signal by the programmable phase comparator. If the difference in time between the delayed clock signal and the clock signal is greater than the dead time, the first counter is triggered. If the difference in time is negative and the absolute value is greater than the dead time, the second counter is triggered. A statistical distribution, based on the values of the counters, is created. This distribution is used to predict on-chip, cycle-to-cycle jitter.

    摘要翻译： 本发明提供一种用于测量片上，周期到周期，抖动的方法和电路。 包括可编程延迟线，可编程相位比较器和两个计数器的电路的副本被放置在靠近时钟信号的IC上的不同位置处。 可编程延迟线产生延迟一个时钟周期的时钟信号。 该延迟时钟信号在可编程相位比较器上与原始时钟信号在时间上进行比较。 如果延迟时钟信号和时钟信号之间的时间差大于死区时间，则触发第一个计数器。 如果时间差为负，绝对值大于死区时间，则触发第二个计数器。 创建基于计数器值的统计分布。 该分布用于预测片上，周期到周期的抖动。

    System and method for evaluating the speed of a circuit
    8.
    发明申请
    System and method for evaluating the speed of a circuit 审中-公开
    用于评估电路速度的系统和方法

    公开(公告)号：US20050007154A1

    公开(公告)日：2005-01-13

    申请号：US10614309

    申请日：2003-07-07

    申请人： Benjamin Patella ,  Eric Fetzer

    发明人： Benjamin Patella ,  Eric Fetzer

    IPC分类号： G01R31/30 ,  G01R31/317 ,  H03K5/135 ,  H03D3/00

    CPC分类号： G01R31/3016 ,  G01R31/3172 ,  G01R31/31725 ,  H03K5/135

    摘要： A method and system for evaluating the speed of a circuit are provided. In accordance with one embodiment, the method comprises determining during a first operational phase of a first operational cycle the propagation speed of a first signal in a first signal propagation path, and concurrently preventing all signals from propagating in a second signal propagation path substantially parallel with the first signal propagation path. The method further comprises determining during a second operational phase alternating with the first operational phase the propagation speed of a second signal in the second signal propagation path, and concurrently preventing all signals from propagating in the first signal propagation path.

    摘要翻译： 提供了一种用于评估电路速度的方法和系统。 根据一个实施例，该方法包括在第一操作周期的第一操作阶段期间确定第一信号传播路径中的第一信号的传播速度，并且同时防止所有信号在与第二信号传播路径基本平行的第二信号传播路径中传播 第一信号传播路径。 该方法还包括在与第一操作阶段交替的第二操作阶段期间确定第二信号传播路径中的第二信号的传播速度，并同时防止所有信号在第一信号传播路径中传播。

    Managing Power Consumption In A Multi-Core Processor
    9.
    发明申请
    Managing Power Consumption In A Multi-Core Processor 有权
    管理多核处理器中的功耗

    公开(公告)号：US20120254643A1

    公开(公告)日：2012-10-04

    申请号：US13422476

    申请日：2012-03-16

    申请人： Eric Fetzer ,  Reid J. Reidlinger ,  Don Soltis ,  William J. Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    发明人： Eric Fetzer ,  Reid J. Reidlinger ,  Don Soltis ,  William J. Bowhill ,  Satish Shrimali ,  Krishnakanth Sistla ,  Efraim Rotem ,  Rakesh Kumar ,  Vivek Garg ,  Alon Naveh ,  Lokesh Sharma

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

    摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

    Receiver and method for mitigating temporary logic transitions
    10.
    发明申请
    Receiver and method for mitigating temporary logic transitions 有权
    用于缓解临时逻辑转换的接收器和方法

    公开(公告)号：US20050270082A1

    公开(公告)日：2005-12-08

    申请号：US11089576

    申请日：2004-06-07

    申请人： Lei Wang ,  Eric Fetzer

    发明人： Lei Wang ,  Eric Fetzer

    IPC分类号： G06F17/50 ,  H03K17/00 ,  H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0292 ,  G06F17/5045 ,  H03K19/00361

    摘要： A circuit and method for receiving data signals over a data signal line are disclosed. In one embodiment, a receiver circuit is provided for receiving data signals transmitted over a signal line. The receiver circuit comprises an inverter circuit having an input that forms an input of the receiver circuit and an output coupled to an internal node, an output circuit having an input coupled to the internal node and an output that provides an output of the receiver circuit, and a charge adding circuit that provides at least a portion of a temporary logic transition at the input of the receiver circuit, induced by a logic transition on an adjacent signal line, to the internal node to mitigate erroneous logic transitions associated with the receiver circuit.

    摘要翻译： 公开了一种通过数据信号线接收数据信号的电路和方法。 在一个实施例中，提供接收器电路用于接收通过信号线传输的数据信号。 接收器电路包括一个反相器电路，该反相器电路具有形成接收器电路的输入和耦合到内部节点的输出的输入端，具有耦合到内部节点的输入的输出电路和提供接收器电路的输出的输出， 以及充电添加电路，其将由接收器电路的输入端引起的临时逻辑转换的至少一部分提供给内部节点，以缓解与接收器电路相关联的错误逻辑转换。