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    Power estimation based on power characterizations of non-conventional circuits
    1.
    发明申请
    Power estimation based on power characterizations of non-conventional circuits 审中-公开
    基于非常规电路的功率特性的功率估计

    公开(公告)号：US20050050494A1

    公开(公告)日：2005-03-03

    申请号：US10653328

    申请日：2003-09-02

    申请人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

    发明人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F2217/78

    摘要： Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations to determine power consumption associated with non-conventional circuits in the circuit design. The power characterizations can be determined prior to circuit design timing analysis, stored and utilized during circuit design timing analysis. The power estimates associated with the non-conventional circuits can be added to power estimates associated with the conventional circuits of the circuit design to compute a power associated with the circuit design.

    摘要翻译： 提供了可用于估计与电路设计相关联的功率的系统和方法。 通过使用功率特征来确定在电路设计中与非常规电路相关联的功率消耗来确定估计功率。 功率特征可以在电路设计时序分析之前确定，在电路设计时序分析期间存储和利用。 与非常规电路相关联的功率估计可以被添加到与电路设计的常规电路相关联的功率估计，以计算与电路设计相关联的功率。

    System and method for measuring current
    2.
    发明申请
    System and method for measuring current 失效
    用于测量电流的系统和方法

    公开(公告)号：US20050040901A1

    公开(公告)日：2005-02-24

    申请号：US10644542

    申请日：2003-08-20

    申请人： Christopher Bostak ,  Samuel Naffziger ,  Christopher Poirier ,  Eric Fetzer

    发明人： Christopher Bostak ,  Samuel Naffziger ,  Christopher Poirier ,  Eric Fetzer

    IPC分类号： G01R31/28 ,  G01R19/00 ,  G01R19/252 ,  H03B1/00

    CPC分类号： G01R19/252 ,  G01R19/0092

    摘要： The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

    摘要翻译： 本发明涉及一种用于测量集成电路中的电流的系统和方法，包括使用第一测量电压测量来自第一压控振荡器（VCO）的第一输出计数，同时使用第二测量电压测量来自第二VCO的第二输出计数 第二测量电压，并且使用与第一和第二输出计数之间的差成比例的电压来计算集成电路中的电流。

    System toTemporarily Modify an Output Waveform
    5.
    发明申请
    System toTemporarily Modify an Output Waveform 失效
    系统暂时修改输出波形

    公开(公告)号：US20050040870A1

    公开(公告)日：2005-02-24

    申请号：US10646936

    申请日：2003-08-22

    申请人： Samuel Naffziger ,  Eric Fetzer

    发明人： Samuel Naffziger ,  Eric Fetzer

    IPC分类号： G01R31/28 ,  G01R31/319 ,  H03K5/06 ,  H03K19/0185 ,  H03K4/90

    CPC分类号： H03K5/06 ,  G01R31/2856 ,  G01R31/31928 ,  H03K19/018585

    摘要： Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.

    摘要翻译： 公开了用于提供临时修改的输出的系统和方法。 波形控制提供在第一操作模式期间临时调整到正常高电平和低电平之间的中间电平的控制输出。 波形控制提供控制输出以在第二操作模式期间在高电平和低电平之间周期性地跳变。 延迟网络控制波形控制，以在第一操作模式期间的中间级提供输出持续一段时间。

    Voltage modulation for increased reliability in an integrated circuit
    7.
    发明授权
    Voltage modulation for increased reliability in an integrated circuit 有权
    电压调制可提高集成电路的可靠性

    公开(公告)号：US07447919B2

    公开(公告)日：2008-11-04

    申请号：US10818974

    申请日：2004-04-06

    申请人： Steven F. Liepe ,  Samuel Naffziger

    发明人： Steven F. Liepe ,  Samuel Naffziger

    IPC分类号： G06F1/00 ,  G06F11/00

    CPC分类号： H03K19/0008 ,  G06F11/00

    摘要： Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F

    摘要翻译： 公开了用于增加集成电路的可靠性的技术。 在一个实施例中，集成电路包括核心芯片电路。 集成电路包括用于增加提供给核心芯片电路的电源电压V的装置，例如通过将电压V增加到最大值。 集成电路还包括用于识别其中C是开关电容的时钟频率F的装置，其中P < max 是核心芯片电路的预定最大功耗。 集成电路还包括用于向电路提供具有频率F的时钟信号的装置。

    Soft-error rate improvement in a latch using low-pass filtering
    8.
    发明申请
    Soft-error rate improvement in a latch using low-pass filtering 有权
    使用低通滤波的锁存器中的软错误率改进

    公开(公告)号：US20060279343A1

    公开(公告)日：2006-12-14

    申请号：US11152274

    申请日：2005-06-13

    申请人： Samuel Naffziger

    发明人： Samuel Naffziger

    IPC分类号： H03K3/356

    CPC分类号： H03K3/0375 ,  H03K3/356104

    摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

    摘要翻译： 在优选实施例中，本发明提供了用于减少锁存器中的软错误事件的电路和方法。 在正向逆变器的输出端和反馈保持器的输入端之间放置一个低通滤波器。 低通滤波器的第一和第二输出分别连接到反馈保持器的第一和第二输入端。 连接到低通滤波器的第一输出的唯一类型的扩散是P型扩散。 连接到低通滤波器的第二输出的唯一类型的扩散是N型扩散。 反馈控制器连接到正向逆变器的输入。

    Count calibration for synchronous data transfer between clock domains
    9.
    发明申请
    Count calibration for synchronous data transfer between clock domains 失效
    对时钟域之间的同步数据传输进行计数校准

    公开(公告)号：US20060248367A1

    公开(公告)日：2006-11-02

    申请号：US11118600

    申请日：2005-04-29

    申请人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

    发明人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12

    摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

    摘要翻译： 公开了用于实现时钟域之间同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。

    Responding to DC power degradation
    10.
    发明申请
    Responding to DC power degradation 有权

    公开(公告)号：US20060069928A1

    公开(公告)日：2006-03-30

    申请号：US10951179

    申请日：2004-09-27

    申请人： Bradley Winick ,  Samuel Naffziger

    发明人： Bradley Winick ,  Samuel Naffziger

    IPC分类号： G06F1/26

    CPC分类号： G06F1/305

    摘要： Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One exemplary frequency scalable processor includes a voltage regulating logic configured to request that a direct current having a reference voltage be provided to the processor. The example processor may also include a logic for detecting whether the voltage matches the reference voltage to within a desired tolerance and to selectively store processor state and/or data based on the detecting.