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1.发明申请Power estimation based on power characterizations of non-conventional circuits 审中-公开基于非常规电路的功率特性的功率估计公开(公告)号：US20050050494A1
公开(公告)日：2005-03-03
申请号：US10653328
申请日：2003-09-02
申请人： Tyson McGuffin , Thomas Chen , Samuel Naffziger , Eric Fetzer
发明人： Tyson McGuffin , Thomas Chen , Samuel Naffziger , Eric Fetzer
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations to determine power consumption associated with non-conventional circuits in the circuit design. The power characterizations can be determined prior to circuit design timing analysis, stored and utilized during circuit design timing analysis. The power estimates associated with the non-conventional circuits can be added to power estimates associated with the conventional circuits of the circuit design to compute a power associated with the circuit design.
摘要翻译： 提供了可用于估计与电路设计相关联的功率的系统和方法。 通过使用功率特征来确定在电路设计中与非常规电路相关联的功率消耗来确定估计功率。 功率特征可以在电路设计时序分析之前确定，在电路设计时序分析期间存储和利用。 与非常规电路相关联的功率估计可以被添加到与电路设计的常规电路相关联的功率估计，以计算与电路设计相关联的功率。
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公开(公告)号：US20050231259A1
公开(公告)日：2005-10-20
申请号：US11155064
申请日：2005-06-17
申请人： Eric Fetzer , Samuel Naffziger , Benjamin Patella
发明人： Eric Fetzer , Samuel Naffziger , Benjamin Patella
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.
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公开(公告)号：US20050099210A1
公开(公告)日：2005-05-12
申请号：US10704252
申请日：2003-11-07
申请人： Eric Fetzer , Samuel Naffziger , Benjamin Patella
发明人： Eric Fetzer , Samuel Naffziger , Benjamin Patella
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.
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公开(公告)号：US20050040901A1
公开(公告)日：2005-02-24
申请号：US10644542
申请日：2003-08-20
IPC分类号： G01R31/28 , G01R19/00 , G01R19/252 , H03B1/00
CPC分类号： G01R19/252 , G01R19/0092
摘要： The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.
摘要翻译： 本发明涉及一种用于测量集成电路中的电流的系统和方法，包括使用第一测量电压测量来自第一压控振荡器（VCO）的第一输出计数，同时使用第二测量电压测量来自第二VCO的第二输出计数 第二测量电压，并且使用与第一和第二输出计数之间的差成比例的电压来计算集成电路中的电流。
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公开(公告)号：US20050040870A1
公开(公告)日：2005-02-24
申请号：US10646936
申请日：2003-08-22
申请人： Samuel Naffziger , Eric Fetzer
发明人： Samuel Naffziger , Eric Fetzer
IPC分类号： G01R31/28 , G01R31/319 , H03K5/06 , H03K19/0185 , H03K4/90
CPC分类号： H03K5/06 , G01R31/2856 , G01R31/31928 , H03K19/018585
摘要： Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and low levels during a first operating mode. The waveform control provides the control output to transition periodically between the high and low levels during a second operating mode. A delay network controls the waveform control to provide the output at the intermediate level for a duration during the first operating mode.
摘要翻译： 公开了用于提供临时修改的输出的系统和方法。 波形控制提供在第一操作模式期间临时调整到正常高电平和低电平之间的中间电平的控制输出。 波形控制提供控制输出以在第二操作模式期间在高电平和低电平之间周期性地跳变。 延迟网络控制波形控制，以在第一操作模式期间的中间级提供输出持续一段时间。
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公开(公告)号：US20110218779A1
公开(公告)日：2011-09-08
申请号：US12718594
申请日：2010-03-05
摘要： A plurality of sequential nodes in a design file for an electronic device are identified and one or more combinatorial power metric values are computed for the plurality of sequential nodes based upon an effective switching capacitance, a switching activity measure, and a power effort measure for at least a first device downstream from the each sequential node at a specified depth. The combinatorial power metric values for the plurality of sequential node are stored and compared to a target power metric value to determine if power consumption at the electronic device meets a predetermined power performance goal.
摘要翻译： 识别用于电子设备的设计文件中的多个顺序节点，并且基于有效开关电容，切换活动度量和用于在线的功率测量措施来为多个顺序节点计算一个或多个组合功率量度值 至少一个在指定深度处从每个顺序节点下游的第一设备。 存储多个顺序节点的组合功率度量值并将其与目标功率度量值进行比较，以确定电子设备的功耗是否满足预定功率性能目标。
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7.发明授权公开(公告)号：US08006115B2
公开(公告)日：2011-08-23
申请号：US10679725
申请日：2003-10-06
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.
摘要翻译： 本发明的一个实施例在中央处理单元的每个时钟区域中包括至少一个传感器，其生成指示时钟区域内的电源电压的功率信号，用于向时钟区域提供可变频率时钟的时钟发生器 以及控制器，用于响应于功率信号和响应于来自其它时钟频带的频率调整通信来控制时钟发生器的工作频率。
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公开(公告)号：US20070096789A1
公开(公告)日：2007-05-03
申请号：US11261337
申请日：2005-10-28
申请人： Jayen Desai , Samuel Naffziger
发明人： Jayen Desai , Samuel Naffziger
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03L7/07 , H03L7/081 , H03L7/0814
摘要： A method of generating a clock signal using a digital frequency synthesizer includes providing a base clock to the digital frequency synthesizer, comparing a phase of an output clock from the digital frequency synthesizer with a phase of a reference signal, and issuing at least one frequency control command to the digital frequency synthesizer to align the phases.
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公开(公告)号：US20060167657A1
公开(公告)日：2006-07-27
申请号：US11040394
申请日：2005-01-21
IPC分类号： G06F11/30
CPC分类号： G06F1/3203 , G06F1/28
摘要： Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.
摘要翻译： 公开了用于维持集成电路性能的系统和方法。 系统的一个实施例可以包括工作功率限制评估器，其确定作为与影响集成电路的性能的变化相关联的至少一个性能因素的函数的工作功率极限。 该系统还可以包括功率管理系统，其基于工作功率极限和集成电路的实际功率来改变集成电路的功率以维持基本上恒定的性能。
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公开(公告)号：US20060083341A1
公开(公告)日：2006-04-20
申请号：US10968735
申请日：2004-10-19
申请人： Samuel Naffziger , Steven Liepe
发明人： Samuel Naffziger , Steven Liepe
IPC分类号： H04L7/00
CPC分类号： H03K5/15046
摘要： One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.
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