公开(公告)号：US09748266B1

公开(公告)日：2017-08-29

申请号：US15215080

申请日：2016-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Liang Pang ,  Ching-Huang Lu ,  Matthias Baenninger ,  Yingda Dong

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28282 ,  H01L27/1157

Abstract: A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.

公开(公告)号：US10381083B1

公开(公告)日：2019-08-13

申请号：US16018018

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kun-Huan Shih ,  Matthias Baenninger ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.

公开(公告)号：US10777570B2

公开(公告)日：2020-09-15

申请号：US15990037

申请日：2018-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Jin Liu ,  Kazuya Tokunaga ,  Marika Gunji-Yoneoka ,  Matthias Baenninger ,  Hiroyuki Kinoshita ,  Murshed Chowdhury ,  Jiyin Xu

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L49/02

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20180277567A1

公开(公告)日：2018-09-27

申请号：US15990037

申请日：2018-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Jin Liu ,  Kazuya Tokunaga ,  Marika Gunji-Yoneoka ,  Matthias Baenninger ,  Hiroyuki Kinoshita ,  Murshed Chowdhury ,  Jiyin Xu

IPC: H01L27/11582 ,  H01L49/02 ,  H01L23/31 ,  H01L23/29 ,  H01L21/764 ,  H01L29/423 ,  H01L23/528 ,  H01L29/10 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US09991280B2

公开(公告)日：2018-06-05

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Jin Liu ,  Kazuya Tokunaga ,  Marika Gunji-Yoneoka ,  Matthias Baenninger ,  Hiroyuki Kinoshita ,  Murshed Chowdhury ,  Jiyin Xu ,  Dai Iwata ,  Hiroyuki Ogawa ,  Kazutaka Yoshizawa ,  Yasuaki Yonemochi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L49/02

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.