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    Method of writing and reading data in an NVM using Lpage identification headers
    1.
    发明授权
    Method of writing and reading data in an NVM using Lpage identification headers 有权

    公开(公告)号：US11449252B2

    公开(公告)日：2022-09-20

    申请号：US16923655

    申请日：2020-07-08

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

    Abstract: A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.

    RETENTION-DRIFT-HISTORY-BASED NON-VOLATILE MEMORY READ THRESHOLD OPTIMIZATION
    2.
    发明申请
    RETENTION-DRIFT-HISTORY-BASED NON-VOLATILE MEMORY READ THRESHOLD OPTIMIZATION 审中-公开

    公开(公告)号：US20200013471A1

    公开(公告)日：2020-01-09

    申请号：US16577789

    申请日：2019-09-20

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen ,  Hao Zhong

    IPC: G11C16/34 ,  G11C29/02 ,  G11C16/04 ,  G11C16/26 ,  G01R19/00 ,  G11C16/28

    Abstract: Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.

    Fractional redundant array of silicon independent elements
    3.
    发明授权
    Fractional redundant array of silicon independent elements 有权

    公开(公告)号：US09727414B2

    公开(公告)日：2017-08-08

    申请号：US13675874

    申请日：2012-11-13

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1096

    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).

    SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE
    4.
    发明申请
    SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE 审中-公开

    公开(公告)号：US20170161191A1

    公开(公告)日：2017-06-08

    申请号：US14611258

    申请日：2015-02-01

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Earl T. Cohen ,  Timothy L. Canepa

    IPC: G06F12/0815

    CPC classification number: G06F12/0815 ,  G06F11/07 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/621 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C16/02 ,  G11C16/06

    Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

    Decoding based on randomized hard decisions
    7.
    发明授权
    Decoding based on randomized hard decisions 有权
    基于随机硬判决进行解码

    公开(公告)号：US09553612B2

    公开(公告)日：2017-01-24

    申请号：US14607492

    申请日：2015-01-28

    Applicant: Seagate Technology LLC

    Inventor： Anatoli A. Bolotov ,  Earl T. Cohen ,  Elyar Gasanov ,  Mikhail I. Grinchuk ,  Pavel A. Panteleev

    IPC: H03M13/00 ,  H03M13/45 ,  H03M13/15

    CPC classification number: H03M13/451 ,  H03M13/152 ,  H03M13/458

    Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.

    Abstract translation: 公开了一种具有存储器和控制器的装置。 存储器被配置为存储码字。 控制器被配置为（i）响应于不能解码码字的硬判决版本，确定码字的软判决版本中的一个或多个最不可靠的比特位置，（ii）通过选择生成试用码字 随机地在硬判决代码字中的最不可靠的位位置中的一个或多个试用位置中的相应值，以及（iii）执行试用码字的硬判决解码。

    Dynamic per-decoder control of log likelihood ratio and decoding parameters
    8.
    发明授权
    Dynamic per-decoder control of log likelihood ratio and decoding parameters 有权
    动态每解码器控制对数似然比和解码参数

    公开(公告)号：US09495244B2

    公开(公告)日：2016-11-15

    申请号：US14967933

    申请日：2015-12-14

    Applicant: Seagate Technology LLC

    Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

    IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

    Abstract: An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information.

    Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 通常使能至少一个处理器来向一个或多个纠错解码器发送消息。 消息可以包含与要由一个或多个纠错解码器解码的缓冲器中的数据相对应的数据路径控制信息。 通常，一个或多个错误校正解码器能够根据相应的数据路径控制信息解码从缓冲器读取的数据。

    Soft-decision compensation for flash channel variation
    10.
    发明授权
    Soft-decision compensation for flash channel variation 有权
    闪光通道变化的软判决补偿

    公开(公告)号：US09483347B2

    公开(公告)日：2016-11-01

    申请号：US14507126

    申请日：2014-10-06

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Yunxiang Wu ,  Earl T. Cohen

    IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G11C29/52

    Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.

    Abstract translation: 在从闪速存储器读取的SSD控制器中，在基于标称LLR的初始软判决解码尝试失败之后，使用在相应读取中预先计算的补偿LLR软判决信息集进行软判决重新解码尝试 - 平衡点对应于闪存通道的实际电荷状态分布中的平均偏移和方差变化。 根据实施例，在不进行重试读取的情况下执行软判定重新解码尝试，或者与一次或多次重试读取重叠。 通过与一次或多次重试读取重新重新解码，成功解码的概率增加，进一步重试读取的需要减少，并且提高了吞吐量。 LLR补偿在大量重试读取中变得非常有效，即使存在大的通道变化，提高了解码的可靠性并实现了接近最佳的误码率。

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