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    Methods of operating image sensors
    1.
    发明授权
    Methods of operating image sensors 有权

    公开(公告)号：US10602086B2

    公开(公告)日：2020-03-24

    申请号：US14883453

    申请日：2015-10-14

    申请人： Seung-Hyuk Chang ,  Yoon-Dong Park ,  Yong-Jei Lee

    发明人： Seung-Hyuk Chang ,  Yoon-Dong Park ,  Yong-Jei Lee

    IPC分类号： H04N5/351 ,  H04N5/225 ,  H04N13/254 ,  H04N13/271 ,  G01S7/481 ,  G01S17/06

    摘要： A method of operating a three-dimensional image sensor may include: obtaining position information of an object using light emitted by a light source module, the three-dimensional image sensor including the light source module having a light source and a lens; and adjusting a relative position of the light source to the lens based on the obtained position information of the object. A method of operating an image sensor may include: obtaining position information of an object using light emitted by a light source module, the image sensor including the light source module; and adjusting an emission angle of the light emitted by the light source module based on the obtained position information.

    IMAGE-SENSING DEVICES AND METHODS OF OPERATING THE SAME
    2.
    发明申请
    IMAGE-SENSING DEVICES AND METHODS OF OPERATING THE SAME 有权
    图像感测装置及其操作方法

    公开(公告)号：US20130020463A1

    公开(公告)日：2013-01-24

    申请号：US13550838

    申请日：2012-07-17

    申请人： Tae-Yon Lee ,  Yoon-Dong Park ,  Yong-Jei Lee ,  Seoung-Hyun Kim ,  Joo-Yeong Gong ,  Sung-Kwon Hong

    发明人： Tae-Yon Lee ,  Yoon-Dong Park ,  Yong-Jei Lee ,  Seoung-Hyun Kim ,  Joo-Yeong Gong ,  Sung-Kwon Hong

    IPC分类号： G01J1/44

    CPC分类号： H04N5/357 ,  H04N5/3696 ,  H04N5/3745 ,  H04N5/378

    摘要： In a method of operating an image sensor, a noise voltage of a floating diffusion region is sampled after a reset voltage is applied to the floating diffusion region. A storage region, in which a photo-charge is stored, is electrically connected to the floating diffusion region after sampling the noise voltage, and a demodulation voltage of the floating diffusion region is sampled after the storage region and the floating diffusion region are electrically-connected. A voltage is determined based on the noise voltage and the demodulation voltage.

    摘要翻译： 在操作图像传感器的方法中，在对浮动扩散区域施加复位电压之后，对浮动扩散区域的噪声电压进行采样。 在对噪声电压进行采样之后，存储光电荷的存储区域与浮动扩散区域电连接，并且在存储区域和浮动扩散区域电气化之后对浮动扩散区域的解调电压进行采样， 连接的。 基于噪声电压和解调电压确定电压。

    Pixel Circuit, depth sensor having dual operating mode for high and low incident light and operating method
    4.
    发明授权
    Pixel Circuit, depth sensor having dual operating mode for high and low incident light and operating method 有权
    像素电路，深度传感器具有双重工作模式，用于高低入射光和操作方法

    公开(公告)号：US08835826B2

    公开(公告)日：2014-09-16

    申请号：US13611607

    申请日：2012-09-12

    申请人： Yong-Jei Lee ,  Yoon-Dong Park ,  Young-Gu Jin

    发明人： Yong-Jei Lee ,  Yoon-Dong Park ,  Young-Gu Jin

    IPC分类号： H01L27/00 ,  G01J1/02 ,  G01S17/89 ,  G01J1/18 ,  G01J1/44 ,  G01S7/491 ,  H04N5/369

    CPC分类号： G01J1/44 ,  G01J1/0228 ,  G01J1/18 ,  G01S7/4914 ,  G01S17/89 ,  H04N5/3696

    摘要： A pixel circuit for a depth sensor operating in a detection period and an output period in either a first operating mode (high incident light intensity) or a second operating mode (low incident light intensity). The pixel circuit includes a light receiving unit generating charge in response to the incident light, a signal generation unit accumulating charge in a FDN in response to a transmission signal, reset signal and selection signal during the detection period, and generating an analog signal having a level corresponding to a voltage apparent at the FDN during the output period, and a refresh transistor coupled between a supply voltage and the light receiving unit and discharging charge to the supply voltage in response to a refresh signal.

    摘要翻译： 用于在第一操作模式（高入射光强度）或第二操作模式（低入射光强度）中的检测周期和输出周期中操作的深度传感器的像素电路。 像素电路包括响应于入射光而产生电荷的光接收单元，信号生成单元响应于在检测周期期间的发送信号，复位信号和选择信号在FDN中累积电荷，并且生成具有 对应于在输出周期期间在FDN处显现的电压的电平，以及耦合在电源电压和光接收单元之间的刷新晶体管，并且响应于刷新信号将电荷放电到电源电压。

    Methods of Operating a Three-Dimensional Image Sensor Including a Plurality of Depth Pixels
    5.
    发明申请
    Methods of Operating a Three-Dimensional Image Sensor Including a Plurality of Depth Pixels 审中-公开
    包含多个深度像素的三维图像传感器的操作方法

    公开(公告)号：US20120236121A1

    公开(公告)日：2012-09-20

    申请号：US13420862

    申请日：2012-03-15

    申请人： Yoon-Dong Park ,  Eric R. Fossum

    发明人： Yoon-Dong Park ,  Eric R. Fossum

    IPC分类号： H04N13/02

    CPC分类号： H04N13/271 ,  H04N13/254

    摘要： In a method of operating a three-dimensional image sensor according to example embodiments, modulated light is emitted to an object of interest, the modulated light that is reflected from the object of interest is detected using a plurality of depth pixels, and a plurality of pixel group outputs respectively corresponding to a plurality of pixel groups are generated based on the detected modulated light by grouping the plurality of depth pixels into the plurality of pixel groups including a first pixel group and a second pixel group that have different sizes from each other.

    摘要翻译： 在根据示例性实施例的操作三维图像传感器的方法中，调制光被发射到感兴趣的对象，使用多个深度像素来检测从感兴趣对象反射的调制光，并且多个 通过将多个深度像素分组为包括彼此不同大小的第一像素组和第二像素组的多个像素组，基于检测到的调制光来生成分别对应于多个像素组的像素组输出。

    Memory device including resistance change layer as storage node and method(s) for making the same
    7.
    发明授权
    Memory device including resistance change layer as storage node and method(s) for making the same 有权
    存储器件包括作为存储节点的电阻变化层及其制造方法

    公开(公告)号：US07507674B2

    公开(公告)日：2009-03-24

    申请号：US11270565

    申请日：2005-11-10

    申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    IPC分类号： H01L21/461

    CPC分类号： H01L27/24 ,  Y10S438/947

    摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.

    摘要翻译： 提供一种用于制造包括根据本发明的示例性实施例的作为存储节点的电阻变化层的存储器件的方法和由该方法制造的存储器件。 根据本发明的示例性实施例，该方法可以包括在底层上层叠（顺序地或以其他方式）导电材料层，二极管层和数据存储层，在数据存储层上形成第一材料层，形成 第一孔暴露第一材料层中的数据存储层，在第一孔的侧壁上形成具有第二材料层的第一间隔物，用第三材料层填充第一孔并覆盖第一间隔物; 去除所述第一材料层，在所述第一间隔物的侧壁上形成具有第四材料层的第二间隔物; 去除第三材料层，并且使用第一和第二间隔件作为掩模，形成以第一堆叠结构暴露底层的第二孔。 这些操作可能导致如所描述的位线和字线的形成。

    Semiconductor device having gate-all-around structure and method of fabricating the same
    9.
    发明申请
    Semiconductor device having gate-all-around structure and method of fabricating the same 有权
    具有栅极全绕结构的半导体器件及其制造方法

    公开(公告)号：US20070181959A1

    公开(公告)日：2007-08-09

    申请号：US11653863

    申请日：2007-01-17

    申请人： Yoon-Dong Park ,  Suk-Pil Kim

    发明人： Yoon-Dong Park ,  Suk-Pil Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/78639

    摘要： Semiconductor devices having a gate-all-around (GAA) structure capable of higher operating performance may be provided. A semiconductor device may include a semiconductor substrate, at least one gate electrode, and at least one gate insulating layer. The semiconductor substrate may have a body, at least one supporting post protruding from the body, and at least one pair of fins separated from the body, wherein both ends of each fin of the at least one pair of fins are connected to and supported by the at least one supporting post. The at least one gate electrode may enclose a portion of at least one fin of the at least one pair of fins of the semiconductor substrate, and may be insulated from the semiconductor substrate. The at least one gate insulating layer may be interposed between the at least one gate electrode and the at least one pair of fins of the semiconductor substrate.

    摘要翻译： 可以提供具有能够具有更高操作性能的全能（GAA）结构的半导体器件。 半导体器件可以包括半导体衬底，至少一个栅电极和至少一个栅极绝缘层。 半导体衬底可以具有本体，从主体突出的至少一个支撑柱和与主体分离的至少一对翅片，其中至少一对翅片的每个翅片的两端连接并由其支撑 所述至少一个支撑柱。 至少一个栅电极可以包围半导体衬底的至少一对散热片中的至少一个鳍片的一部分，并且可以与半导体衬底绝缘。 所述至少一个栅极绝缘层可以插入在所述至少一个栅电极和所述半导体衬底的所述至少一对鳍之间。

    Memory device including resistance change layer as storage node and method(s) for making the same
    10.
    发明申请
    Memory device including resistance change layer as storage node and method(s) for making the same 有权

    公开(公告)号：US20060110877A1

    公开(公告)日：2006-05-25

    申请号：US11270565

    申请日：2005-11-10

    申请人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    发明人： Yoon-Dong Park ,  Won-Joo Kim ,  Sang-Hun Jeon

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/24 ,  Y10S438/947

    摘要： A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask. These operations may result in the formation of bit lines and word lines as described.