公开(公告)号：US08293820B2

公开(公告)日：2012-10-23

申请号：US11875800

申请日：2007-10-19

申请人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

发明人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

IPC分类号： C08L63/02

CPC分类号： C25D13/06 ,  C09D5/4496 ,  C25D13/16

摘要： A cationic electrodeposition coating composition comprising a cationic resin (A) and a blocked polyisocyanate (B) obtained by reaction between a polyisocyanate compound (b1) with two or more isocyanate groups, castor oil (b2) and a blocking agent (b3). The cationic electrodeposition coating composition has excellent throwing power, suitability for electrodeposition onto hot dip galvanized steel sheets, finished appearance and corrosion resistance.

摘要翻译： 一种阳离子电沉积涂料组合物，其包含阳离子树脂（A）和通过多异氰酸酯化合物（b1）与两个或多个异氰酸酯基团反应获得的封端多异氰酸酯（B），蓖麻油（b2）和封闭剂（b3）。 阳离子电沉积涂料组合物具有优异的抛光力，适用于电沉积到热镀锌钢板上，成品外观和耐腐蚀性。

公开(公告)号：US20080099342A1

公开(公告)日：2008-05-01

申请号：US11875800

申请日：2007-10-19

申请人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

发明人： Shigeo Nishiguchi ,  Hideki Iijima ,  Naoyuki Yoshikawa ,  Kiyoshi Kato ,  Yukihiro Nemoto ,  Reijirou Nishida

IPC分类号： C25D9/02

CPC分类号： C25D13/06 ,  C09D5/4496 ,  C25D13/16

摘要： A cationic electrodeposition coating composition comprising a cationic resin (A) and a blocked polyisocyanate (B) obtained by reaction between a polyisocyanate compound (b1) with two or more isocyanate groups, castor oil (b2) and a blocking agent (b3). The cationic electrodeposition coating composition has excellent throwing power, suitability for electrodeposition onto hot dip galvanized steel sheets, finished appearance and corrosion resistance.

摘要翻译： 一种阳离子电沉积涂料组合物，其包含阳离子树脂（A）和通过多异氰酸酯化合物（b1）与两个或多个异氰酸酯基团反应获得的封端多异氰酸酯（B），蓖麻油（b2）和封闭剂（b3）。 阳离子电沉积涂料组合物具有优异的抛光力，适用于电沉积到热镀锌钢板上，成品外观和耐腐蚀性。

公开(公告)号：US20090234048A1

公开(公告)日：2009-09-17

申请号：US12382337

申请日：2009-03-13

申请人： Kiyoshi Kato ,  Naoyuki Yoshikawa

发明人： Kiyoshi Kato ,  Naoyuki Yoshikawa

IPC分类号： C08L1/00

CPC分类号： C09D17/005 ,  C09D5/4438 ,  C09D5/4473 ,  C09D5/448

摘要： The present invention provides a pigment dispersion paste with improved storage stability, and an electrodeposition coating composition that enables energy saving in electrodeposition coating equipment and a reduction in the amount of electrodeposition coating equipment.The pigment dispersion paste of the present invention contains (i) a pigment-dispersing resin, (ii) a pigment component, (iii) a cellulose (A), (iv) a hydroxyalkyl imidazoline compound (B) and/or a compound (C), and (v) water;the pigment dispersion paste containing, per 100 parts by mass of the solids of the pigment-dispersing resin, 0.1 to 1,000 parts by mass of the pigment component, 0.1 to 25 parts by mass of the cellulose (A), 0.1 to 5 parts by mass of a hydroxyalkyl imidazoline compound (B) and/or 0.1 to 5 parts by mass of a compound (C); andthe pigment dispersion paste having, when adjusted to a solids concentration of 40 mass %, an TI value of 1.8 to 4.0 as measured by the pigment test method of JIS K 5101-6-2: wherein R1 is a C6-32 hydrocarbon group and R2 is a C2-6 alkylene group; wherein n is an integer from 11 to 16.

摘要翻译： 本发明提供了一种具有改善的储存稳定性的颜料分散膏，以及能够在电沉积涂布设备中节能和减少电沉积涂布设备的电沉积涂料组合物。 本发明的颜料分散膏包含（i）颜料分散树脂，（ii）颜料成分，（iii）纤维素（A），（iv）羟烷基咪唑啉化合物（B）和/或化合物 C），（v）水; 颜料分散糊剂，相对于100质量份颜料分散性树脂的固体，将0.1〜1000质量份的颜料成分，0.1〜25质量份的纤维素（A），0.1〜5份的 羟烷基咪唑啉化合物（B）的质量和/或0.1〜5质量份的化合物（C）; 并且当调节为40质量％的固体浓度时，通过JIS K 5101-6-2的颜料测试方法测量的TI值为1.8至4.0的颜料分散糊：其中R1是C6-32烃基 R2是C2-6亚烷基; 其中n为11至16的整数。

公开(公告)号：US20160274965A1

公开(公告)日：2016-09-22

申请号：US15166485

申请日：2016-05-27

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/07

CPC分类号： G06F11/079 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/3452 ,  G06Q10/02

摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

公开(公告)号：US09384079B2

公开(公告)日：2016-07-05

申请号：US14589255

申请日：2015-01-05

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06Q10/02 ,  G06F11/34

CPC分类号： G06F11/079 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/3452 ,  G06Q10/02

摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

公开(公告)号：US09188631B2

公开(公告)日：2015-11-17

申请号：US13446614

申请日：2012-04-13

申请人： Kiyoshi Kato ,  Konami Izumi ,  Masahiko Hayakawa ,  Koichiro Kamata

发明人： Kiyoshi Kato ,  Konami Izumi ,  Masahiko Hayakawa ,  Koichiro Kamata

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/302 ,  H01L27/13

CPC分类号： G01R31/2822 ,  G01R31/2886 ,  G01R31/3025 ,  H01L27/13

摘要： A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit.

摘要翻译： 提供了包括可以以高可靠性评估元件的特性的半导体层的基板及其评价方法。 包括本发明的半导体层的衬底具有一个闭环电路，其中天线线圈和半导体元件串联连接，并且形成有电路的区域的表面被绝缘膜覆盖。 通过使用这样的电路，可以进行非接触检查。 此外，环形振荡器可以代替闭环电路。

公开(公告)号：US08946710B2

公开(公告)日：2015-02-03

申请号：US13358554

申请日：2012-01-26

申请人： Kiyoshi Kato ,  Takeshi Osada

发明人： Kiyoshi Kato ,  Takeshi Osada

IPC分类号： H01L29/04 ,  H01L27/13 ,  H03K3/03 ,  H03K5/13 ,  H03K23/58 ,  H03L7/085 ,  H03L7/099 ,  H03L7/18 ,  H01L27/12 ,  H03K5/00

CPC分类号： H01L27/13 ,  H01L27/1214 ,  H01L27/1266 ,  H03K3/0315 ,  H03K5/133 ,  H03K23/582 ,  H03K2005/00039 ,  H03K2005/00202 ,  H03L7/085 ,  H03L7/0995 ,  H03L7/18

摘要： A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved.

摘要翻译： 具有功能高，功能多，附加值高的半导体器件。 半导体器件包括提供在衬底上并且输出具有正确频率的信号的PLL电路。 通过在衬底上设置这样的PLL电路，可以实现具有高功能，多功能和高附加值的半导体器件。

公开(公告)号：US08896046B2

公开(公告)日：2014-11-25

申请号：US13285450

申请日：2011-10-31

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  H01L27/06 ,  H01L27/12

CPC分类号： H01L27/108 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

摘要： Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.

摘要翻译： 提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入次数没有限制。 半导体器件包括包括氧化物半导体（在更广泛的意义上是截止电流足够小的晶体管）的晶体管的存储器电路和包括晶体管的诸如驱动器电路的外围电路，该晶体管包括除了 氧化物半导体（即，能够以足够高的速度运行的晶体管）。 此外，外围电路设置在下部，并且存储电路设置在上部，使得可以减小半导体器件的面积和尺寸。

公开(公告)号：US08779433B2

公开(公告)日：2014-07-15

申请号：US13115239

申请日：2011-05-25

申请人： Atsuo Isobe ,  Yoshinori Ieda ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

发明人： Atsuo Isobe ,  Yoshinori Ieda ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC分类号： H01L29/10 ,  H01L27/115 ,  H01L27/108

CPC分类号： H01L27/10852 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入数量没有限制。 半导体器件包括设置在第一晶体管上的第二晶体管和电容器。 使用具有相对于栅电极的蚀刻选择性的材料形成与第一晶体管的栅电极接触的第二晶体管的源电极。 通过使用相对于第一晶体管的栅电极具有蚀刻选择性的材料形成第二晶体管的源电极，可以减小布局的裕度，从而可以提高半导体器件的集成度。

公开(公告)号：US08642987B2

公开(公告)日：2014-02-04

申请号：US12578650

申请日：2009-10-14

申请人： Tamae Takano ,  Kiyoshi Kato ,  Hideaki Kuwabara

发明人： Tamae Takano ,  Kiyoshi Kato ,  Hideaki Kuwabara

IPC分类号： H01L45/00

CPC分类号： H01L27/12 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01L51/0595

摘要： The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.

摘要翻译： 本发明提供了一种新颖的存储器，其工艺技术相对简单，并且可以通过少量元件存储多值信息。 使第一存储元件中的第一电极的形状的一部分与第二存储元件中的第一电极的形状不同，从而改变第一电极和第二电极之间改变电阻的电压值，因此 一个存储单元存储超过一位的多值信息。 通过部分地处理第一电极，可以增加每单位面积的存储容量。