公开(公告)号：US08780629B2

公开(公告)日：2014-07-15

申请号：US13004942

申请日：2011-01-12

申请人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

发明人： Kazuma Furutani ,  Yoshinori Ieda ,  Yuto Yakubo ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC分类号： G11C11/34 ,  G11C11/24 ,  G11C16/04 ,  H01L29/788

CPC分类号： H01L27/1214 ,  G11C11/403 ,  G11C16/0425 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

摘要翻译： 半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态下具有小的漏电流，读取晶体管包括与写入晶体管不同的半导体材料， 和电容器。 通过接通写入晶体管并将数据写入或重写到存储器单元中，并将电位施加到写入晶体管的源极和漏极，电容器的一个电极和读取的晶体管的栅电极之一的节点 彼此电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。

公开(公告)号：US08319269B2

公开(公告)日：2012-11-27

申请号：US12143472

申请日：2008-06-20

申请人： Yoshinori Ieda

发明人： Yoshinori Ieda

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/78621

摘要： A decease in reliability of a memory element having a floating gate is suppressed. The invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate. The first insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.

摘要翻译： 抑制了具有浮动栅极的存储元件的可靠性的下降。 本发明涉及一种具有岛状半导体膜的半导体器件，其形成在绝缘表面上并且包括沟道形成区域和高浓度杂质区域，形成在岛状半导体膜上的隧道绝缘膜， 在栅极绝缘膜上形成的栅极绝缘膜，形成在栅极绝缘膜上的控制栅极以及形成在隧道绝缘膜和浮动栅极之间的第一绝缘膜。 第一绝缘膜由浮栅的材料的氧化膜形成，从而防止浮栅的材料扩散到隧道绝缘膜中。

公开(公告)号：US20110316057A1

公开(公告)日：2011-12-29

申请号：US13161871

申请日：2011-06-16

申请人： Motomu KURATA ,  Shinya SASAGAWA ,  Fumika TAGUCHI ,  Yoshinori IEDA

发明人： Motomu KURATA ,  Shinya SASAGAWA ,  Fumika TAGUCHI ,  Yoshinori IEDA

IPC分类号： H01L29/78 ,  H05K1/00 ,  H01L21/3213 ,  H01L21/321

CPC分类号： H01L27/1288 ,  H01L21/31053 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/486 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

摘要翻译： 本发明的目的是减少集成度增加的布线板或半导体器件的导通不良。 另一个目的是以高产率制造高度可靠的布线板或半导体器件。 在具有多层布线结构的布线板或半导体器件中，具有弯曲表面的导电层用于连接用于布线的导电层。 通过去除其周围的绝缘层而暴露的下层中的导电层的顶部具有弯曲表面，使得下层中的导电层与其上层叠的上层中的导电层的覆盖率是有利的。 使用具有弯曲表面的抗蚀剂掩模蚀刻导电层，从而形成具有弯曲表面的导电层。

公开(公告)号：US08901554B2

公开(公告)日：2014-12-02

申请号：US13484742

申请日：2012-05-31

申请人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Yoshinori Ieda

发明人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Yoshinori Ieda

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66969 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/47573 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/7869

摘要： A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.

摘要翻译： 与氧化物半导体膜和第二绝缘膜接触的第一绝缘膜依次层叠在包含氧化物半导体膜的晶体管的电极膜上，在第二绝缘膜上形成蚀刻掩模， 通过蚀刻第一绝缘膜的一部分和第二绝缘膜的一部分形成电极膜，将暴露于电极膜的开口部暴露于氩等离子体中，除去蚀刻掩模，并且在开口中形成导电膜 部分暴露电极膜。 第一绝缘膜是其氧气通过加热部分释放的绝缘膜。 第二绝缘膜比第一绝缘膜不易蚀刻，并且具有比第一绝缘膜更低的透气性。

公开(公告)号：US08569753B2

公开(公告)日：2013-10-29

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

发明人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC分类号： H01L21/02

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US08319267B2

公开(公告)日：2012-11-27

申请号：US12943532

申请日：2010-11-10

申请人： Kiyoshi Kato ,  Yoshinori Ieda ,  Jun Koyama

发明人： Kiyoshi Kato ,  Yoshinori Ieda ,  Jun Koyama

IPC分类号： H01L29/788

CPC分类号： H01L27/12 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/77 ,  H01L27/11521 ,  H01L27/1225 ,  H01L29/42324 ,  H01L29/7881

摘要： A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.

摘要翻译： 提供了包括新颖的非易失性存储元件的装置。 包括其中使用氧化物半导体作为沟道形成区域的半导体材料的非易失性存储元件的器件。 非易失性存储元件包括控制栅极，与控制栅极重叠的电荷累积层，其间设置有第一绝缘膜，以及使用氧化物半导体材料形成的氧化物半导体层，其与电荷累积层重叠，具有第二绝缘 膜之间。

公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

发明人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20110156023A1

公开(公告)日：2011-06-30

申请号：US12974254

申请日：2010-12-21

申请人： Yoshinori IEDA

发明人： Yoshinori IEDA

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/24

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/42328 ,  H01L29/7881

摘要： In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.

摘要翻译： 在使用非易失性存储器的半导体器件中，实现了高速擦除操作和低功耗。 在其中依次层叠沟道形成区域，隧道绝缘膜和浮置栅极的非易失性存储器中，使用氧化物半导体层形成沟道形成区域。 此外，用于擦除的金属布线设置在沟道形成区域的下侧以便面对浮动栅极。 利用上述结构，当执行擦除操作时，通过沟道形成区域向金属布线提取在浮动栅极中累积的电荷。 因此，可以实现半导体器件的高速擦除操作和低功耗。

公开(公告)号：US09437454B2

公开(公告)日：2016-09-06

申请号：US13161871

申请日：2011-06-16

申请人： Motomu Kurata ,  Shinya Sasagawa ,  Fumika Taguchi ,  Yoshinori Ieda

发明人： Motomu Kurata ,  Shinya Sasagawa ,  Fumika Taguchi ,  Yoshinori Ieda

IPC分类号： H01L29/10 ,  H01L21/3213 ,  H01L27/12

CPC分类号： H01L27/1288 ,  H01L21/31053 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/486 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed.

摘要翻译： 本发明的目的是减少集成度增加的布线板或半导体器件的导通不良。 另一个目的是以高产率制造高度可靠的布线板或半导体器件。 在具有多层布线结构的布线板或半导体器件中，具有弯曲表面的导电层用于连接用于布线的导电层。 通过去除其周围的绝缘层而暴露的下层中的导电层的顶部具有弯曲表面，使得下层中的导电层与其上层叠的上层中的导电层的覆盖率可能是有利的。 使用具有弯曲表面的抗蚀剂掩模蚀刻导电层，从而形成具有弯曲表面的导电层。

公开(公告)号：US09111795B2

公开(公告)日：2015-08-18

申请号：US13444124

申请日：2012-04-11

申请人： Yoshinori Ieda ,  Atsuo Isobe ,  Yutaka Shionoiri ,  Tomoaki Atsumi

发明人： Yoshinori Ieda ,  Atsuo Isobe ,  Yutaka Shionoiri ,  Tomoaki Atsumi

IPC分类号： H01L27/108 ,  H01L27/115 ,  H01L27/105 ,  H01L49/02 ,  H01L27/12

CPC分类号： H01L27/1207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/40 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/7869

摘要： Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.

摘要翻译： 提供具有低功耗并且可以高速运行的半导体器件。 半导体器件包括：存储元件，其包括在沟道形成区域中包括晶体硅的第一晶体管，用于存储存储元件的数据的电容器;以及第二晶体管，其是用于控制电荷的供应，存储和释放的开关元件 电容器。 第二晶体管设置在覆盖第一晶体管的绝缘膜上。 第一和第二晶体管共同地具有源电极或漏电极。