公开(公告)号：US11057029B2

公开(公告)日：2021-07-06

申请号：US16694100

申请日：2019-11-25

Applicant: Silicon Laboratories Inc.

Inventor： Alan L. Westwick ,  Peter Onody ,  András V. Horváth ,  Tamás Marozsák

IPC: H03K17/16 ,  H03K17/0812 ,  H02P29/024

Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

公开(公告)号：US20210159898A1

公开(公告)日：2021-05-27

申请号：US16694100

申请日：2019-11-25

Applicant: Silicon Laboratories Inc.

Inventor： Alan L. Westwick ,  Peter Onody ,  András V. Horváth ,  Tamás Marozsák

IPC: H03K17/16 ,  H03K17/0812 ,  H02P29/024

Abstract: A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

公开(公告)号：US20220115941A1

公开(公告)日：2022-04-14

申请号：US17066251

申请日：2020-10-08

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Fernando Naim Lavalle Aviles ,  Carlos Jesus Briseno-Vidrios ,  Patrick De Bakker ,  Gabor Marek ,  Charles Guo Lin ,  Peter Onody ,  Tamás Marozsák ,  András V. Horváth

IPC: H02M1/08 ,  H03K17/691 ,  H03K17/18

Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

公开(公告)号：US20210099165A1

公开(公告)日：2021-04-01

申请号：US16588777

申请日：2019-09-30

Applicant: Silicon Laboratories Inc.

Inventor： András V. Horváth ,  Carlos Briseno-Vidrios ,  Viktor Zsolczai ,  Soma Ur

IPC: H03K17/082 ,  G06F1/26 ,  H04L12/10

Abstract: A method for establishing a powered link over a transmission line includes enabling a current source to provide a constant, predetermined current to a terminal. The method includes sensing a voltage on the terminal to generate a sensed voltage level. The method includes comparing the sensed voltage level on the terminal to a predetermined voltage level. The method includes disabling the current source in response to the sensed voltage level equaling or exceeding the predetermined voltage level. The method may include, while the current source is enabled, a power transistor coupled to the terminal is disabled and only conducts current in a subthreshold region of transistor operation.

公开(公告)号：US10469075B2

公开(公告)日：2019-11-05

申请号：US15610009

申请日：2017-05-31

Applicant: Silicon Laboratories Inc.

Inventor： András V. Horváth

IPC: H03K3/00 ,  H03K17/284 ,  H03K17/16

Abstract: A driver circuit has pre-driver and transistor pairs coupled in parallel paths with different delays in different paths allowing the driver to automatically adjust to load conditions, providing a moderate driver with low output ringing for low capacitive loads, while the added delay in the different paths is negligible when driving heavy capacitive loads. The driver circuit automatically scales drive strength of the output driver during switching transients to the load capacitance, providing a good trade-off between fast transient and low output ringing for a variety of different capacitive loads.

公开(公告)号：US20180351546A1

公开(公告)日：2018-12-06

申请号：US15610009

申请日：2017-05-31

Applicant: Silicon Laboratories Inc.

Inventor： András V. Horváth

IPC: H03K17/284 ,  H03K17/16

Abstract: A driver circuit has pre-driver and transistor pairs coupled in parallel paths with different delays in different paths allowing the driver to automatically adjust to load conditions, providing a moderate driver with low output ringing for low capacitive loads, while the added delay in the different paths is negligible when driving heavy capacitive loads. The driver circuit automatically scales drive strength of the output driver during switching transients to the load capacitance, providing a good trade-off between fast transient and low output ringing for a variety of different capacitive loads.

公开(公告)号：US11258432B1

公开(公告)日：2022-02-22

申请号：US17125561

申请日：2020-12-17

Applicant: Silicon Laboratories Inc.

Inventor： Péter Onódy ,  András V. Horváth

IPC: H03K5/125 ,  H03K5/1252 ,  H03H11/06 ,  H03H11/26 ,  H03K3/012 ,  H03K17/687 ,  H03K19/20

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

公开(公告)号：US20180348295A1

公开(公告)日：2018-12-06

申请号：US15609996

申请日：2017-05-31

Applicant: Silicon Laboratories Inc.

Inventor： Ernest T. Stroud ,  Stefan N. Mastovich ,  Huanhui Zhan ,  Tamás Marozsák ,  András V. Horváth

IPC: G01R31/28

Abstract: An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.