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公开(公告)号：US20240347491A1
公开(公告)日：2024-10-17
申请号：US18202360
申请日：2023-05-26
Applicant: SITRONIX TECHNOLOGY CORP.
Inventor： Kuo-Wei Tseng
CPC classification number: H01L24/13 , H01L24/11 , H01L23/3171 , H01L24/16 , H01L2224/11462 , H01L2224/1147 , H01L2224/1308 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225
Abstract: The present application discloses a bump structure and a manufacturing method thereof. The bump structure comprises a first bump layer disposed on a chip and a second bump layer disposed on the first bump layer, and the hardness of the first and second bump layers are different, and both materials of the first and second bump layers are the same conductive material. Thus, when the chip is connected with a substrate through the bump structure and a force applied to the bump structure, it is not easily to cause that the bump structure makes a damage on the chip, and the bump structure according to the present invention is to enhance the structure characteristic and prevented from damaging.
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公开(公告)号：US11694983B2
公开(公告)日：2023-07-04
申请号：US17444233
申请日：2021-08-02
Applicant: SITRONIX TECHNOLOGY CORP.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
CPC classification number: H01L24/13 , H01L22/32 , H01L24/06 , H01L24/14 , H01L2224/0603 , H01L2224/10145 , H01L2224/13013 , H01L2224/13023 , H01L2224/1403 , H01L2224/14051 , H01L2224/14133
Abstract: The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.
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公开(公告)号：US20200335474A1
公开(公告)日：2020-10-22
申请号：US16916136
申请日：2020-06-30
Applicant: Sitronix Technology Corp.
Inventor： Ying-Chen Chang , Po-Chi Chen , Kuo-Wei Tseng
IPC: H01L23/00
Abstract: A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.
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公开(公告)号：US20190115285A1
公开(公告)日：2019-04-18
申请号：US16161318
申请日：2018-10-16
Applicant: Sitronix Technology Corp
Inventor： Kuo-Wei Tseng , Po-Chi Chen , Jui-Hsuan Cheng
IPC: H01L23/495 , H01L23/00
Abstract: The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.
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公开(公告)号：US20180114769A1
公开(公告)日：2018-04-26
申请号：US15792767
申请日：2017-10-25
Applicant: Sitronix Technology Corp.
Inventor： Ying-Chen Chang , Po-Chi Chen , Kuo-Wei Tseng
CPC classification number: H01L24/81 , H01L23/49811 , H01L23/49838 , H01L23/4985 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L2224/0401 , H01L2224/05567 , H01L2224/13007 , H01L2224/13013 , H01L2224/13019 , H01L2224/13021 , H01L2224/13144 , H01L2224/16013 , H01L2224/16014 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16238 , H01L2224/16502 , H01L2224/73253 , H01L2224/81097 , H01L2224/81193 , H01L2224/81345 , H01L2224/81444 , H01L2224/81447 , H01L2224/81805 , H01L2924/00014
Abstract: A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.
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Patent Agency Ranking
公开(公告)号：US20170345784A1
公开(公告)日：2017-11-30
申请号：US15675783
申请日：2017-08-13
Applicant: Sitronix Technology Corp.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L2224/11
Abstract: The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure.
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公开(公告)号：US11217508B2
公开(公告)日：2022-01-04
申请号：US16161318
申请日：2018-10-16
Applicant: Sitronix Technology Corp
Inventor： Kuo-Wei Tseng , Po-Chi Chen , Jui-Hsuan Cheng
IPC: H01L23/495 , H01L23/00 , H01L23/498 , H01L23/60
Abstract: The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.
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公开(公告)号：US10163769B2
公开(公告)日：2018-12-25
申请号：US15675783
申请日：2017-08-13
Applicant: Sitronix Technology Corp.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
IPC: H01L29/40 , H01L23/498 , H01L23/00
Abstract: The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure.
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公开(公告)号：US09773746B2
公开(公告)日：2017-09-26
申请号：US15190147
申请日：2016-06-22
Applicant: Sitronix Technology Corp.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
IPC: H01L29/40 , H01L21/44 , H01L23/00 , H01L23/498
CPC classification number: H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17
Abstract: An electronic element for an electronic apparatus includes a substrate; a bump, disposed on the substrate for electrically connecting the electronic apparatus; and at least one under bump metal layer, disposed between the bump and the substrate for the bump to be attached to the substrate; wherein the UBM layer forms a breach structure.
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公开(公告)号：US20160379949A1
公开(公告)日：2016-12-29
申请号：US15190147
申请日：2016-06-22
Applicant: Sitronix Technology Corp.
Inventor： Kuo-Wei Tseng , Po-Chi Chen
IPC: H01L23/00
CPC classification number: H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17
Abstract: An electronic element for an electronic apparatus includes a substrate; a bump, disposed on the substrate for electrically connecting the electronic apparatus; and at least one under bump metal layer, disposed between the bump and the substrate for the bump to be attached to the substrate; wherein the UBM layer forms a breach structure.
Abstract translation: 一种电子设备用电子元件，包括：基板; 凸起，设置在所述基板上，用于电连接所述电子设备; 以及设置在所述凸块和所述基板之间的至少一个下凸块金属层，用于所述凸块附接到所述基板; 其中UBM层形成破裂结构。
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